Prototype Header - Xilinx ZCU102 User Manual

Table 3-31: XCZU9EG U1 to PMOD Connections
XCZU9EG Schematic Net
(U1) Pin
A20 PMOD0_0
B20 PMOD0_1
A22 PMOD0_2
PMOD0_3
A21
B21 PMOD0_4
C21 PMOD0_5
PMOD0_6
C22
PMOD0_7
D21
D20 PMOD1_0
E20 PMOD1_1
PMOD1_2
D22
E22 PMOD1_3
F20 PMOD1_4
PMOD1_5
G20
J20 PMOD1_6
J19 PMOD1_7
For more information about PMOD connector compatible PMOD modules, see

Prototype Header

[Figure 2-1, callout 41]
The ZCU102 evaluation board provides a 2x12 male header prototype header J3 which
makes ten Bank 50 GPIO connections available.
MPSoC (U1) Bank 50 connections.
ZCU102 Evaluation Board User Guide
UG1182 (v1.2) March 20, 2017
I/O Standard
Name
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
www.xilinx.com
Chapter 3: Board Component Descriptions
PMOD Pin
J55.1
J55.3
J55.5
J55.7
J55.2
J55.4
J55.6
J55.8
J87.1
J87.3
J87.5
J87.7
J87.2
J87.4
J87.6
J77.8
Figure 3-29 shows connector J3 with its
[Ref 23].
72
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