Xilinx ZCU102 User Manual page 25

The ZCU102 supports full power-off suspend mode where only the system controller and
the PS-side DDR4 SODIMM memory are powered. The DDR4 memory is kept in a
self-refresh state and has its reset input controlled by the system controller such that the
memory is not reset when waking-up from suspend mode. DDR4 SODIMM standard right
angle Socket J1 connections are identified in
Table 3-3: DDR4 SODIMM Socket J1 Connections to FPGA PS DDR Bank 504
XCZU9EG
(U1) Pin
AP29 DDR4_SODIMM_A0
AP30 DDR4_SODIMM_A1
AP26 DDR4_SODIMM_A2
AP27
DDR4_SODIMM_A3
AP25 DDR4_SODIMM_A4
AN24 DDR4_SODIMM_A5
AM29
DDR4_SODIMM_A6
AM28 DDR4_SODIMM_A7
AM26 DDR4_SODIMM_A8
AM25 DDR4_SODIMM_A9
AL28
DDR4_SODIMM_A10
AK27 DDR4_SODIMM_A11
AJ25 DDR4_SODIMM_A12
AL25 DDR4_SODIMM_A13
AH26
DDR4_SODIMM_BA0
AG26 DDR4_SODIMM_BA1
AK28 DDR4_SODIMM_BG0
AH27
DDR4_SODIMM_BG1
AP20 DDR4_SODIMM_DQ0
AP18 DDR4_SODIMM_DQ1
AP19
DDR4_SODIMM_DQ2
AP17 DDR4_SODIMM_DQ3
AM20 DDR4_SODIMM_DQ4
AM19 DDR4_SODIMM_DQ5
AM18
DDR4_SODIMM_DQ6
AL18 DDR4_SODIMM_DQ7
AP22 DDR4_SODIMM_DQ8
AP21 DDR4_SODIMM_DQ9
AP24
DDR4_SODIMM_DQ10
ZCU102 Evaluation Board User Guide
UG1182 (v1.2) March 20, 2017
Net Name
Pin Number
www.xilinx.com
Chapter 3:
Table 3-3.
DDR4 SODIMM Memory J1
Pin Name
144 A0
133 A1
132 A2
131 A3
128 A4
126 A5
127 A6
122 A7
125 A8
121 A9
146 A10/AP
120 A11
119 A12
158 A13
150 BA0
145 BA1
115 BG0
113 BG1
8 DQ0
7 DQ1
20 DQ2
21 DQ3
4 DQ4
3 DQ5
16 DQ6
17 DQ7
28 DQ8
29 DQ9
41 DQ10
Board Component Descriptions
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