Xilinx ZCU102 User Manual page 90

Table 3-41: XCZU9EG Interconnect Matrix
Protocol
PCIe
SATA
USB0
USB1
DisplayPort
SGMII0
SGMII1
SGMII2
SGMII3
Table 3-42: Interconnect Matrix Settings and GTR Lane Functionality
Protocol
Power down
PCIe
SATA
USB
DisplayPort
SGMII
The GTR selections provided with GT switch topology shown in
1. PCIe Gen2/1 x4
2. DisplayPort (2-Lanes), USB, SATA
3. PCIe Gen2/1 x2, USB, SATA
4. PCIe Gen2/1 x1, DisplayPort (1-Lane), USB, SATA
ZCU102 Evaluation Board User Guide
UG1182 (v1.2) March 20, 2017
PHY Lane 0 PHY Lane 1
PCIe.0 PCIe.0
SATA.0 SATA.1
USB0 USB0
DP.1 DP.0
SGMII0
SGMII1
Values
3'h0
3'h1
3'h2
3'h3
3'h4
3'h5
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Chapter 3: Board Component Descriptions
PHY Lane 2 PHY Lane 3
PCIe.0 PCIe.0
SATA.0 SATA.1
USB0
USB1
DP.1 DP.0
SGMII2
SGMII3
Figure 3-37
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