Xilinx ZCU102 User Manual page 119

#Other net
#Other net
#Other net
#Other net
#Other net
#Other net
#Other net
#Other net
#Other net
#Other net
#Other net
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#Other net
#Other net
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#Other net
#Other net
#Other net
#DDR4 COMPONENT 16-BIT U2
set_property PACKAGE_PIN AM8
set_property IOSTANDARD SSTL12_DCI
set_property PACKAGE_PIN AM9
set_property IOSTANDARD SSTL12_DCI
set_property PACKAGE_PIN AP8
set_property IOSTANDARD SSTL12_DCI
set_property PACKAGE_PIN AN8
set_property IOSTANDARD SSTL12_DCI
set_property IOSTANDARD SSTL12_DCI
set_property PACKAGE_PIN AJ10
set_property IOSTANDARD SSTL12_DCI
set_property PACKAGE_PIN AP9
set_property IOSTANDARD SSTL12_DCI
set_property PACKAGE_PIN AN9
set_property IOSTANDARD SSTL12_DCI
set_property PACKAGE_PIN AP10
set_property IOSTANDARD SSTL12_DCI
set_property PACKAGE_PIN AP11
set_property IOSTANDARD SSTL12_DCI
set_property PACKAGE_PIN AM10
set_property IOSTANDARD SSTL12_DCI
set_property PACKAGE_PIN AL10
set_property IOSTANDARD SSTL12_DCI
set_property PACKAGE_PIN AM11
set_property IOSTANDARD SSTL12_DCI
set_property PACKAGE_PIN AL11
set_property IOSTANDARD SSTL12_DCI
set_property PACKAGE_PIN AJ7
set_property IOSTANDARD SSTL12_DCI
set_property PACKAGE_PIN AL5
set_property IOSTANDARD SSTL12_DCI
set_property PACKAGE_PIN AJ9
set_property IOSTANDARD SSTL12_DCI
set_property PACKAGE_PIN AK12
set_property IOSTANDARD SSTL12_DCI
set_property PACKAGE_PIN AJ12
ZCU102 Evaluation Board User Guide
UG1182 (v1.2) March 20, 2017
PACKAGE_PIN AN19 - DDR4_SODIMM_DQS0_C
PACKAGE_PIN AN22 - DDR4_SODIMM_DQS1_C
PACKAGE_PIN AJ19 - DDR4_SODIMM_DQS2_C
PACKAGE_PIN AH23 - DDR4_SODIMM_DQS3_C
PACKAGE_PIN AH29 - DDR4_SODIMM_DQS4_C
PACKAGE_PIN AE29 - DDR4_SODIMM_DQS5_C
PACKAGE_PIN AK32 - DDR4_SODIMM_DQS6_C
PACKAGE_PIN AE33 - DDR4_SODIMM_DQS7_C
PACKAGE_PIN AN33 - DDR4_SODIMM_DQS8_C
PACKAGE_PIN AN18 - DDR4_SODIMM_DQS0_T
PACKAGE_PIN AN21 - DDR4_SODIMM_DQS1_T
PACKAGE_PIN AH19 - DDR4_SODIMM_DQS2_T
PACKAGE_PIN AH22 - DDR4_SODIMM_DQS3_T
PACKAGE_PIN AH28 - DDR4_SODIMM_DQS4_T
PACKAGE_PIN AE28 - DDR4_SODIMM_DQS5_T
PACKAGE_PIN AJ32 - DDR4_SODIMM_DQS6_T
PACKAGE_PIN AE32 - DDR4_SODIMM_DQS7_T
PACKAGE_PIN AN32 - DDR4_SODIMM_DQS8_T
PACKAGE_PIN AM30
PACKAGE_PIN AJ26
PACKAGE_PIN AF20 - DDR4_SODIMM_PARITY
www.xilinx.com
Appendix B:
- DDR4_SODIMM_ODT0
- DDR4_SODIMM_ODT1
[get_ports "DDR4_A0"]
[get_ports "DDR4_A0"]
[get_ports "DDR4_A1"]
[get_ports "DDR4_A1"]
[get_ports "DDR4_A2"]
[get_ports "DDR4_A2"]
[get_ports "DDR4_A3"]
[get_ports "DDR4_A3"]
[get_ports "DDR4_A4"]
[get_ports "DDR4_A5"]
[get_ports "DDR4_A5"]
[get_ports "DDR4_A6"]
[get_ports "DDR4_A6"]
[get_ports "DDR4_A7"]
[get_ports "DDR4_A7"]
[get_ports "DDR4_A8"]
[get_ports "DDR4_A8"]
[get_ports "DDR4_A9"]
[get_ports "DDR4_A9"]
[get_ports "DDR4_A10"]
[get_ports "DDR4_A10"]
[get_ports "DDR4_A11"]
[get_ports "DDR4_A11"]
[get_ports "DDR4_A12"]
[get_ports "DDR4_A12"]
[get_ports "DDR4_A13"]
[get_ports "DDR4_A13"]
[get_ports "DDR4_A14_WE_B"]
[get_ports "DDR4_A14_WE_B"]
[get_ports "DDR4_A15_CAS_B"]
[get_ports "DDR4_A15_CAS_B"]
[get_ports "DDR4_A16_RAS_B"]
[get_ports "DDR4_A16_RAS_B"]
[get_ports "DDR4_BA0"]
[get_ports "DDR4_BA0"]
[get_ports "DDR4_BA1"]
Master Constraints File Listing
Bank 504 - PS_DDR_DQS_N0
Bank 504 - PS_DDR_DQS_N1
Bank 504 - PS_DDR_DQS_N2
Bank 504 - PS_DDR_DQS_N3
Bank 504 - PS_DDR_DQS_N4
Bank 504 - PS_DDR_DQS_N5
Bank 504 - PS_DDR_DQS_N6
Bank 504 - PS_DDR_DQS_N7
Bank 504 - PS_DDR_DQS_N8
Bank 504 - PS_DDR_DQS_P0
Bank 504 - PS_DDR_DQS_P1
Bank 504 - PS_DDR_DQS_P2
Bank 504 - PS_DDR_DQS_P3
Bank 504 - PS_DDR_DQS_P4
Bank 504 - PS_DDR_DQS_P5
Bank 504 - PS_DDR_DQS_P6
Bank 504 - PS_DDR_DQS_P7
Bank 504 - PS_DDR_DQS_P8
Bank 504 - PS_DDR_ODT0
Bank 504 - PS_DDR_ODT1
Bank 504 - PS_DDR_PARITY
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