Uart0 (Mio 18-19); Uart1 (Mio 20-21) - Xilinx ZCU102 User Manual

Table 3-24: I2C1 TCA9548A U135 Multiplexer Connections
U135 I2C Mux
(Addr 0x75) Port
0
1
2
3
4
5
6
7

UART0 (MIO 18-19)

This is the primary Zynq UltraScale+ MPSoC PS-side UART interface and is connected to the
U40 CP2108 USB-to-Quad-UART bridge with port assignments as listed in
PS-side UART0 is accessed through the U40 CP2108 USB-to-Quad-UART bridge port 0.
Use SiLabs CP210X VCP driver version 6.7.0 or later for proper USB enumeration as
IMPORTANT:
identified in Table
Table 3-25: CP2108 UART Assignments
CP2108 U40
PS_UART0 (MIO 18-19)
UART0
UART1 PS_UART1 (MIO 20-21)
UART2 PL-UART (HD Bank 49)
U41 System Controller UART
UART3

UART1 (MIO 20-21)

PS-side UART1 is accessed through the U40 CP2108 USB-to-Quad-UART Bridge port 1. The
CP2108 Channel 1 PS-side UART interface circuit is shown in
from XCZU9EG U1 to CP2108 U40 via L/S U54 are listed in
ZCU102 Evaluation Board User Guide
UG1182 (v1.2) March 20, 2017
I2C BUS 1 Device(s)
FMC HPC_0
FMC HPC_1
SYSMON
DDR4 SODIMM
SFP_3
SFP_2
SFP_1
SFP_0
3-25.
Zynq UltraScale+ MPSoC
www.xilinx.com
Chapter 3: Board Component Descriptions
Figure 3-19. The connections
Table 3-26.
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Table 3-25.
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