Xilinx ZCU102 User Manual page 69

X-Ref Target - Figure 3-26
Table 3-30: XCZU9EG U1 to P2 SFP+ Module Quad-Connector
XCZU9EG
Schematic Net Name
(U1) Pin
E4 SFP0_TX_P
E3 SFP0_TX_N
SFP0_RX_P
D2
D1 SFP0_RX_N
A12 SFP0_TX_DISABLE
D6 SFP1_TX_P
SFP1_TX_N
D5
C4 SFP1_RX_P
C3 SFP1_RX_N
SFP1_TX_DISABLE
A13
SFP2_TX_P
B6
B5 SFP2_TX_N
B2 SFP2_RX_P
SFP2_RX_N
B13
B13 SFP2_TX_DISABLE
ZCU102 Evaluation Board User Guide
UG1182 (v1.2) March 20, 2017
Figure 3-26: Quad-SFP Interface
SFP+ Pin
Location Right Top SFP0
RT18
RT19
RT13
RT12
(1)
RT3
Location Right Lower SFP1
RL18
RL19
RL13
RL12
(1)
RL3
Location Left Top SFP2
LT18
LT19
LT13
LT12
(1) LT3
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Chapter 3: Board Component Descriptions
SFP+ Pin Name
RT_TD_P
RT_TD_N
RT_RD_P
RT_RD_N
RT_ TX_DISABLE
RL_TD_P
RL_TD_N
RL_RD_P
RL_RD_N
RL_ TX_DISABLE
LT_TD_P
LT_TD_N
LT_RD_P
LT_RD_N
LT_ TX_DISABLE
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