I2C0 (Mio 14-15) - Xilinx ZCU102 User Manual

I2C0 (MIO 14-15)

I2C0 connects to MPSoC U1 PS Bank 500 and PL bank 50, and to system controller U41, as
shown in Figure
U97) and an I2C SWITCH (PCA9544A U60) for controlling resets, GTR multiplexer settings,
and power system enable pins, without requiring the PL-side to be configured. TCA6416A
U97 is pin-strapped to respond to I2C address 0x20, and U61 to 0x21. The PCA9544A
multiplexer is set to 0x75.
The I2C0 bus also provides access to the PMBUS power controllers and PS-side and PL-side
INA226 power monitors via the U60 PCA9544A bus switch. All PMBus controlled Maxim
regulators are tied to the MAXIM_PMBUS, while the INA226 power monitors are separated
on to PS_PMBUS and PL_PMBUS.
Table 3-19 lists the I2C0 port expander TCA6416A U61 connections and
TCA6416A U97 connections. The devices on each bus of the I2C0 multiplexer U60 are
identified in Table 3-21
ZCU102 Evaluation Board User Guide
UG1182 (v1.2) March 20, 2017
3-17. I2C0 connects to two GPIO 16-bit port expanders (TCA6416A U61 and
Figure 3-17
and the multiplexer bus connections are listed in
www.xilinx.com
Chapter 3: Board Component Descriptions
shows the I2C0 bus topology.
Table 3-20 the
Table 3-22.
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