Xilinx ZCU102 User Manual page 83

Table 3-35: ZCU102 GTH Bank 128 Interface Connections
XCZU9EG XCZU9EG (U1) Pin
(U1) Pin Name
T29 MGTHTXP0_128
MGTHTXN0_128
T30
MGTHTXP1_128
R31
R32 MGTHTXN1_128
P29 MGTHTXP2_128
MGTHTXN2_128
P30
T33 MGTHRXP0_128
T34 MGTHRXN0_128
P33 MGTHRXP1_128
MGTHRXN1_128
P34
N31 MGTHRXP2_128
N32 MGTHRXN2_128
MGTREFCLK1P_18
N27
N28 MGTREFCLK1N_128
M29 MGTHTXP3_128
M30 MGTHTXN3_128
MGTHRXP3_128
M33
M34 MGTHRXN3_128
R27 MGTREFCLK0P_128
R28 MGTREFCLK0N_128
Notes:
1. Series capacitor coupled.
2. MGT connections I/O standard not applicable.
ZCU102 Evaluation Board User Guide
UG1182 (v1.2) March 20, 2017
(2)
Schematic Net Name
HDMI_TX0_P
HDMI_TX0_N
HDMI_TX1_P
HDMI_TX1_N
HDMI_TX2_P
HDMI_TX2_N
HDMI_RX0_C_P (1)
(1)
HDMI_RX0_C_N
(1)
HDMI_RX1_C_P
HDMI_RX1_C_N (1)
HDMI_RX2_C_P (1)
(1)
HDMI_RX2_C_N
HDMI_RX_CLK_C_P (1)
HDMI_RX_CLK_C_N (1)
SMA_MGT_TX_P
SMA_MGT_TX_N
SMA_MGT_RX_C_P (1)
SMA_MGT_RX_C_N (1)
(1)
HDMI_SI5324_OUT_C_P
(1)
HDMI_SI5324_OUT_C_N
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Chapter 3: Board Component Descriptions
Connected To
Pin No. Pin Name
8 IN_D0P
IN_D0N
9
IN_D1P
5
6 IN_D1N
2 IN_D2P
IN_D2N
3
B7 TMDS_DATA0_P
B9 TMDS_DATA0_N
B4 TMDS_DATA1_P
TMDS_DATA1_N
B6
B1 TMDS_DATA2_P
B3 TMDS_DATA2_N
TMDS_CLK_P
B10
B12 TMDS_CLK_N
1 SIG
1 SIG
SIG
1
1 SIG
28 CKOUT1_P
29 CKOUT1_N
Send Feedback
Device
TI SN65DP159RGZ
HDMI RETIMER
U94
MOLEX HDMI
BOTTOM PORT P7
SMA J71
SMA J72
SMA J69
SMA J70
SI5324C JITTER
ATTEN. U108
83