Xilinx ZCU102 User Manual page 84

Table 3-36 lists GTH bank 129 connections.
Table 3-36: ZCU102 GTH Bank 129 Interface Connections
XCZU9EG XCZU9EG (U1) Pin
(U1) Pin Name
MGTHTXP0_129
K29
K30 MGTHTXN0_129
L31 MGTHRXP0_129
L32 MGTHRXN0_129
MGTHTXP1_129
J31
J32 MGTHTXN1_129
K33 MGTHRXP1_129
MGTHRXN1_129
K34
H29 MGTHTXP2_129
H30 MGTHTXN2_129
H33 MGTHRXP2_129
MGTHRXN2_129
H34
G31 MGTHTXP3_129
G32 MGTHTXN3_129
F33 MGTHRXP3_129
MGTHRXN3_129
F34
L27 MGTREFCLK0P_129
L28 MGTREFCLK0N_129 USER_MGT_SI570_CLOCK1_C_N
MGTREFCLK1P_129
J27
J28 MGTREFCLK1N_129 USER_SMA_MGT_CLOCK_C_N
Notes:
1. Series capacitor coupled.
2. MGT connections I/O standard not applicable.
3. U51 buffer driven by SI570 U56 (156.250 MHz default)
ZCU102 Evaluation Board User Guide
UG1182 (v1.2) March 20, 2017
Schematic Net Name
FMC_HPC1_DP4_C2M_P
FMC_HPC1_DP4_C2M_N
FMC_HPC1_DP4_M2C_P
FMC_HPC1_DP4_M2C_N
FMC_HPC1_DP5_C2M_P
FMC_HPC1_DP5_C2M_N
FMC_HPC1_DP5_M2C_P
FMC_HPC1_DP5_M2C_N
FMC_HPC1_DP6_C2M_P
FMC_HPC1_DP6_C2M_N
FMC_HPC1_DP6_M2C_P
FMC_HPC1_DP6_M2C_N
FMC_HPC1_DP7_C2M_P
FMC_HPC1_DP7_C2M_N
FMC_HPC1_DP7_M2C_P
FMC_HPC1_DP7_M2C_N
USER_MGT_SI570_CLOCK1_C_P
USER_SMA_MGT_CLOCK_C_P
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Chapter 3: Board Component Descriptions
Connected To
(2)
Pin No. Pin Name
DP4_C2M_P
A34
A35 DP4_C2M_N
A14 DP4_M2C_P
A15 DP4_M2C_N
DP5_C2M_P
A38
A39 DP5_C2M_N
A18 DP5_M2C_P
DP5_M2C_N
A19
B36 DP6_C2M_P
B37 DP6_C2M_N
B16 DP6_M2C_P
DP6_M2C_N
B17
B32 DP7_C2M_P
B33 DP7_C2M_N
B12 DP7_M2C_P
DP7_M2C_N
B13
(1) 11 Q1_P
(1)
12 Q1_N
(1) SIG
1
(1) 1 SIG
Device
FMC HPC1 J4
(3)
SI53340
BUFF. U51
J79
J80
84
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