Xilinx ZCU102 User Manual page 120

set_property IOSTANDARD SSTL12_DCI
set_property PACKAGE_PIN AK4
set_property IOSTANDARD POD12_DCI
set_property PACKAGE_PIN AK5
set_property IOSTANDARD POD12_DCI
set_property PACKAGE_PIN AN4
set_property IOSTANDARD POD12_DCI
set_property PACKAGE_PIN AM4
set_property IOSTANDARD POD12_DCI
set_property PACKAGE_PIN AP4
set_property IOSTANDARD POD12_DCI
set_property PACKAGE_PIN AP5
set_property IOSTANDARD POD12_DCI
set_property PACKAGE_PIN AM5
set_property IOSTANDARD POD12_DCI
set_property PACKAGE_PIN AM6
set_property IOSTANDARD POD12_DCI
set_property PACKAGE_PIN AK2
set_property IOSTANDARD POD12_DCI
set_property PACKAGE_PIN AK3
set_property IOSTANDARD POD12_DCI
set_property PACKAGE_PIN AL1
set_property IOSTANDARD
set_property PACKAGE_PINAK1
set_property IOSTANDARD POD12_DCI
set_property PACKAGE_PIN AN1
set_property IOSTANDARD POD12_DCI
set_property PACKAGE_PIN AM1
set_property IOSTANDARD POD12_DCI
set_property PACKAGE_PIN AP3
set_property IOSTANDARD POD12_DCI
set_property PACKAGE_PIN AN3
set_property IOSTANDARD POD12_DCI
set_property PACKAGE_PIN AP6
set_property IOSTANDARD DIFF_POD12
set_property PACKAGE_PIN AN6
set_property IOSTANDARD DIFF_POD12
set_property PACKAGE_PIN AL2
set_property IOSTANDARD DIFF_POD12
set_property PACKAGE_PIN AL3
set_property IOSTANDARD DIFF_POD12
set_property PACKAGE_PIN AL6
set_property IOSTANDARD POD12_DCI
set_property PACKAGE_PIN AN2
set_property IOSTANDARD POD12_DCI
set_property PACKAGE_PIN AP7
set_property IOSTANDARD DIFF_SSTL12
set_property PACKAGE_PIN AN7
set_property IOSTANDARD DIFF_SSTL12
set_property PACKAGE_PIN AM3
set_property IOSTANDARD SSTL12_DCI
set_property PACKAGE_PIN AK7
set_property IOSTANDARD SSTL12_DCI
set_property PACKAGE_PIN AP1
set_property IOSTANDARD SSTL12_DCI
set_property PACKAGE_PIN AK8
set_property IOSTANDARD SSTL12_DCI
set_property PACKAGE_PIN AK9
set_property IOSTANDARD SSTL12_DCI
ZCU102 Evaluation Board User Guide
UG1182 (v1.2) March 20, 2017
Appendix B:
[get_ports "DDR4_BA1"]
[get_ports "DDR4_DQ0"]
[get_ports "DDR4_DQ0"]
[get_ports "DDR4_DQ1"]
[get_ports "DDR4_DQ1"]
[get_ports "DDR4_DQ2"]
[get_ports "DDR4_DQ2"]
[get_ports "DDR4_DQ3"]
[get_ports "DDR4_DQ3"]
[get_ports "DDR4_DQ4"]
[get_ports "DDR4_DQ4"]
[get_ports "DDR4_DQ5"]
[get_ports "DDR4_DQ5"]
[get_ports "DDR4_DQ6"]
[get_ports "DDR4_DQ6"]
[get_ports "DDR4_DQ7"]
[get_ports "DDR4_DQ7"]
[get_ports "DDR4_DQ8"]
[get_ports "DDR4_DQ8"]
[get_ports "DDR4_DQ9"]
[get_ports "DDR4_DQ9"]
[get_ports "DDR4_DQ10"]
POD12_DCI [get_ports "DDR4_DQ10"]
[get_ports "DDR4_DQ11"]
[get_ports "DDR4_DQ11"]
[get_ports "DDR4_DQ12"]
[get_ports "DDR4_DQ12"]
[get_ports "DDR4_DQ13"]
[get_ports "DDR4_DQ13"]
[get_ports "DDR4_DQ14"]
[get_ports "DDR4_DQ14"]
[get_ports "DDR4_DQ15"]
[get_ports "DDR4_DQ15"]
[get_ports "DDR4_DQS0_C"]
[get_ports "DDR4_DQS0_C"]
[get_ports "DDR4_DQS0_T"]
[get_ports "DDR4_DQS0_T"]
[get_ports "DDR4_DQS1_C"]
[get_ports "DDR4_DQS1_C"]
[get_ports "DDR4_DQS1_T"]
[get_ports "DDR4_DQS1_T"]
[get_ports "DDR4_DM0"]
[get_ports "DDR4_DM0"]
[get_ports "DDR4_DM1"]
[get_ports "DDR4_DM1"]
[get_ports "DDR4_CK_C"]
[get_ports "DDR4_CK_C"]
[get_ports "DDR4_CK_T"]
[get_ports "DDR4_CK_T"]
[get_ports "DDR4_CKE"]
[get_ports "DDR4_CKE"]
[get_ports "DDR4_BG0"]
[get_ports "DDR4_BG0"]
[get_ports "DDR4_PAR"]
[get_ports "DDR4_PAR"]
[get_ports "DDR4_ACT_B"]
[get_ports "DDR4_ACT_B"]
[get_ports "DDR4_ODT"]
[get_ports "DDR4_ODT"]
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