Sd Card Interface - Xilinx ZCU102 User Manual

SD1 (MIO 39-51)
A PS-side interface to an SD card connector is provided for booting and file system storage.
This interface is used for the SD boot mode and supports SD3.0 access post boot.

SD Card Interface

[Figure 2-1, callout 6]
The ZCU102 board includes a secure digital input/output (SDIO) interface to provide access
to general purpose non-volatile SDIO memory cards and peripherals. Information for the
SD I/O card specification can be found at the SanDisk Corporation
Association [Ref 16]
configuration boot mode documented in the Zynq UltraScale+ MPSoC Technical Reference
Manual (UG1085)
The SDIO signals are connected to XCZU9EG MPSoC PS bank 501 which has its V
to 1.8V. Each of the six MIOxx_SDIO_* nets has a series 30 ohm resistor at the source. An
NXP IP4856CX25 SD 3.0-compliant voltage level-translator U133 is present between the
XCZU9EG MPSoC and the SD card connector (J100). The NXP IP4856CX25 U133 device
provides SD3.0 capability with SDR104 performance. The NXP SD3.0 level shifter is mounted
on an Aries adapter board that has the pin mapping shown in
Table 3-9: U133 IP4856CX25 Adapter Pin-Out
Aires Adapter
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ZCU102 Evaluation Board User Guide
UG1182 (v1.2) March 20, 2017
websites. The ZCU102 SD card interface supports the SD1_LS
[Ref 2].
IP4856CX25 U133 IP4856CX25 U133
Pin Number
C1 CLK_IN
C3 GND
CD
D3
D2 CMD_H
E2 CLK_FB
E4 WP
VLDO
B4
C4 V
SD_REF
A3 DIR_0
V
A4
SUPPLY
B3 V
CCA
A2 DIR_CMD
D1 DATA0_H
SEL
B2
B1 DATA3_H
E1 DATA1_H
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Chapter 3:
Pin Name
Board Component Descriptions
[Ref 15] or SD
CCMIO
Table 3-9.
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