Xilinx ZCU102 User Manual page 9

• PS MIO: CAN
• PS MIO: UART (using USB-to-UART bridge)
• PS MIO: Second UART
• PS MIO: I2C shared across PS and PL
• PS/PL EMIO: Trace
• PL-side UART
• PL-side LEDs (8)
• PL-side DIP switch (8-position)
• PL-side Pushbuttons (5)
• PS-side Pushbutton (1)
• PS-side LED (1)
• System User Switches (PROG, CPU Reset)
• PJTAG
• Security - PSBATT button battery backup
• SYSMON
• Operational Switches (Power on/off, PROG, Boot mode)
• Operational Status LEDs (power supply status, INIT, DONE, PG, JTAG status, DDR power
good)
• Power Management
The ZCU102 evaluation board provides designers a rapid prototyping platform utilizing the
XCZU9EG-2FFVB1156I device. The ZU9EG contains many useful processor system (PS) hard
block peripherals exposed through the Multi-use I/O (MIO) interface and a variety of FPGA
programmable logic (PL), high-density (HD) and high-performance (HP) banks.
lists a brief summary of the resources available within the ZU9EG. A feature set overview,
description, and ordering information is provided in the UltraScale Architecture and Product
Overview (DS890)
Table 1-1: Zynq UltraScale+ MPSoC ZCU9EG Features and Resources
Feature
HD banks
HP banks
MIO banks
PS-side GTR 6 Gb/s transceivers
PL-side GTH 16.3 Gb/s transceivers
Effective LEs
ZCU102 Evaluation Board User Guide
UG1182 (v1.2) March 20, 2017
[Ref 1].
5 banks, total of 120 pins
4 banks, total of 208 pins
3 banks, total of 78 pins
4 PS-GTRs
24 GTHs
575K
www.xilinx.com
Resource Count
Chapter 1: Introduction
Table 1-1
9
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