Xilinx ZCU102 User Manual page 66

X-Ref Target - Figure 3-24
Table 3-29: HDMI Retimer U94 Connections to FPGA U1
XCZU9EG
Schematic Net Name
(U1) Pin
T29 HDMI_TX0_P
T30 HDMI_TX0_N
R31 HDMI_TX1_P
HDMI_TX1_N
R32
P29 HDMI_TX2_P
P30 HDMI_TX2_N
HDMI_TX_LVDS_OUT_P
AF6
AG6 HDMI_TX_LVDS_OUT_N
C16 HDMI_TX_SRC_SCL
D16 HDMI_TX_SRC_SDA
HDMI_TX_EN
B15
F15 HDMI_CTL_SCL
F16 HDMI_CTL_SDA
ZCU102 Evaluation Board User Guide
UG1182 (v1.2) March 20, 2017
Figure 3-24: HDMI Interface Circuit
I/O Standard
(1)
(1)
(1)
(1)
(1)
(1)
LVDS
LVDS
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
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Chapter 3: Board Component Descriptions
Connected Component
Pin No. Pin Name
8 IN_D0P
9 IN_D0N
5 IN_D1P
IN_D1N
6
2 IN_D2P
3 IN_D2N
IN_CLKP
11
12 IN_CLKN
46 SCL_SRC
47 SDA_SRC
OE
42
15 SCL_CTL
16 SDA_CTL
Device
SN65DP159
(U94)
(2)
66
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