Revision History - Xilinx ZCU102 User Manual

Revision History

The following table shows the revision history for this document.
Date Version
03/20/2017 1.2
11/16/2016 1.1
05/11/2016 1.0
ZCU102 Evaluation Board User Guide
UG1182 (v1.2) March 20, 2017
Added notes to Dimensions in Chapter
Table 2-2 and SD configuration setting in
settings under Quad-SPI and
heading to "DDR Component Memory" in
from 33 MHz to 33.33 MHz in
"UART2_CTS_O_B" in Table
U120 (UPR)" heading to "MSP430 U41" in
Figure 3-17 in Table 3-19
Table 3-22 and headings in
Table 3-28. Updated GTH connectivity for Quad 128, Quad 228, Quad 229, and
Quad 23 under GTH Transceivers in Chapter
Figure 3-35. Added callout 44 to
Appendix D, Additional Resources and Legal
Updated device part number from XCZU9EG-2FFVB1156 to XCZU9EG-2FFVB1156I
throughout document. Updated board photos
Updated Table 2-1 and Table
Updated Appendix B, Master Constraints File
Initial Xilinx release - limited distribution.
www.xilinx.com
Revision
1. Updated SW6 default switch setting in
Table 2-4. Clarified SW6[4:1] boot mode pin
SD in Chapter 2. Changed "DDR SODIMM Memory J1"
Table 3-4. Changed PS_REF_CLK frequency
Table 3-12. Changed "UART2_RTS_O_B" to
3-16. Replaced Figure 3-16. Changed "QSPI119 (LWR),
Table 3-17. Clarified references to
and Table 3-20. Added addresses to titles in
Table 3-23 and Table 3-24. Changed "22" to "L22" in
3. Updated bank assignments in
Switches in Chapter
Notices.
(Figure 2-1
2-3. Updated Chapter 3, Component
Listing.
Table 3-21
3. Updated Xilinx websites in
and Figure 2-1) to rev 1.0.
Descriptions.
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