Xilinx ZCU102 User Manual page 103

Table 3-53: J4 HPC1 FMC Section J and K Connections to XCZU9EG U1
J5 Pin Schematic Net Name
J2 NC
J3 NC
J6 NC
J7 NC
J9 NC
J10 NC
J12 NC
J13 NC
J15 NC
J16 NC
J18 NC
J19 NC
J21 NC
J22 NC
J24 NC
J25 NC
J27 NC
J28 NC
J30 NC
J31 NC
J33 NC
J34 NC
J36 NC
J37 NC
J39 NC
See the ANSI/VITA 57.1 FPGA mezzanine card (FMC) specification
information on the FPGA FMC.
ZCU102 Evaluation Board User Guide
UG1182 (v1.2) March 20, 2017
I/O
U1 Pin J5 Pin
Standard
K1
K4
K5
K7
K8
K10
K11
K13
K14
K16
K17
K19
K20
K22
K23
K25
K26
K28
K29
K31
K32
K34
K35
K37
K38
K40
www.xilinx.com
Chapter 3: Board Component Descriptions
Schematic Net Name
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
[Ref 22]
I/O
U1 Pin
Standard
for additional
103
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