Ps-Side: Gtr Transceivers - Xilinx ZCU102 User Manual

PS-Side: GTR Transceivers

[Figure 2-1, callout 1]
The PS-side GTR transceivers are shared through on-board bidirectional 2:1
multiplexer/de-multiplexer switches U125-U128 (Pericom PI2DBS6212
6.5 Gb/s operation (see
X-Ref Target - Figure 3-36
Block Diagram
A0+
A0-
A1+
A1-
SEL
Truth Table
Function
A to B
A to C
The external GT-switch selection must be set by the user to ensure consistency with the
ZU9EG's internal GT interconnect matrix (ICM) settings. There are PS-side MIO GPIO(s) that
control the Pericom GT switch settings via PS-side I2C0 and the external GPIO port
expander.
The functionality of each ZU9EG GTR lane is controlled through the MPSoC's ICM and is
defined in the Zynq UltraScale+ MPSoC Technical Reference Manual (UG1085)
Table 3-41 lists the interconnect matrix (ICM).
settings and GTR lane functionality.
ZCU102 Evaluation Board User Guide
UG1182 (v1.2) March 20, 2017
Figure 3-36).
B0+
B0-
B1+
B1-
C0+
C0-
C1+
C1-
SEL
L
H
Figure 3-36: Pericom GTR Switch Block Diagram
www.xilinx.com
Chapter 3: Board Component Descriptions
Pin Description
28 27 26 25
GND 1
NC 2
SEL
3
A0+ 4
A0- 5
A1+ 6
A1-
7
NC 8
9
V
DD
GND 10
11 12 13 14
Table 3-42 lists the interconnect matrix
[Ref 20]) capable of
24 B0+
23 B0-
B1+
22
21 B1-
20 GND
19
V
DD
C0+
18
17 C0-
16 C1+
15 C1-
[Ref 2].
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