I2C1 (Mio 16-17) - Xilinx ZCU102 User Manual

Table 3-22: I2C0 U60 (Addr. 0x75) Mux Target Bus Connections (Cont'd)
Reference
Designation
U16
U65
U74
U75
J84
U47
U7
U6
U10
U9
U63
U95
U96
U46
U4
U18
U13
U49
U8
U1
U135

I2C1 (MIO 16-17)

The PS-side I2C1 interface provides access to I2C peripherals through a set of I2C switches.
The I2C connection is shared with the PL-side and the system controller.
a high-level view of the I2C1 bus connectivity represented in
TCA9548A U34 is set to 0x74 and TCA9548A U135 is set to 0x75.
ZCU102 Evaluation Board User Guide
UG1182 (v1.2) March 20, 2017
Address
INA226 VCC3V3
0X44
INA226 VADJ_FMC
0X45
INA226 MGTAVCC
0X46
INA226 MGTAVTT
0X47
MAXIM_PMBUS
PMBUS Conn SDA Pin 3/SCL Pin 1
N/A
MAX15301 VCCINT
0X13
MAX15303 VCCBRAM
0X14
MAX15303 VCCAUX
5
0X1
MAX15303 VCC1V2
0X16
MAX15303 VCC3V3
0X17
MAX15301 VADJ_FMC
0X18
MAX20751 MGTAVCC
0X72
MAX20751 MGTAVTT
0X73
MAX15301 VCCPSINTFP
0X0A
MAX15303 VCCPSINTLP
0X0B
MAX15303 DDR4_DIMM_VDDQ
0X1D
MAX15303 VCCOPS
0X10
MAX15301 UTIL_3V3
0X1A
MAX15301 UTIL_5V0
0X1B
SYSMON
U1 BANK 49 SDA Pin B14/SCL Pin C14
N/A
N/A TCA9548A Mux I2C1 Bus Port 2
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Chapter 3:
Device(s)
Board Component Descriptions
Figure 3-18
Table 3-23 and Table 3-24.
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