Gpio (Mio 13, 38) - Xilinx ZCU102 User Manual

CP2108 Channel 3 MSP430 UART Interface
The CP2108 Channel 3 MSP430 UART interface circuit is shown in
connections from MSP430 U41 to CP2108 U40 via TSX0104E level shifter U53 are listed in
Table 3-17.
X-Ref Target - Figure 3-16
Table 3-17: MSP430 U41 to CP2108 U40 Connections via L/S U53
MSP430 U41
Pin Name Pin No.
P3_3 26
P3_3 25

GPIO (MIO 13, 38)

These two (2) GPIO bits are connected to the U41 MSP430 system controller for general
purpose signaling or communications between the Zynq UltraScale+ MPSoC device and the
MSP430 system controller. These signals are level-shifted by TSX0108E U141. The
connections between the U41 system controller and the XCZU9EG MPSoC are listed in
Table 3-18.
Table 3-18: System Controller U41 GPIO Connections to XCZU9EG U1
XCZU9EG
(U1) Pin
MIO13_PS_GPIO2
AK17
L23 MIO38_PS_GPIO1
ZCU102 Evaluation Board User Guide
UG1182 (v1.2) March 20, 2017
Figure 3-16: MSP430 USB UART Interface
Schematic Net Name
UART3_TXD_O_MSP430_UCA0_RXD
UART3_RXD_I_MSP430_UCA0_TXD
Net Name
Pin Name
20
19
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Chapter 3:
CP2108 U40
Pin Name Pin No.
TX_3
RX_3
MSP430 U41
Pin No.
P1_7
P1_6
Board Component Descriptions
Figure 3-16. The
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