Intel NIOS II Owner Reference Manual page 59

3. Programming Model
NII-PRG | 2018.04.18
Table 29. config Control Register Field Descriptions
Field
is the automatic nested interrupt mode bit. If
ANI ANI
the processor clears
nested interrupts. If
status.PIE
nested interrupts.
If the EIC interface and shadow register sets are not implemented in
the Nios II core,
interrupts.
ECCEXE ECCEX
Nios II processor generates ECC error exceptions.
ECCEN ECCEN
ignores all ECC errors. When
recovers all recoverable ECC errors.
is the memory protection enable bit. When
PE PE
enabled. When
MPU,
PE
3.4.2.13. The mpubase Register
The
mpubase
retrieve MPU region information and is only available in systems with an MPU.
Table 30. mpubase Control Register Fields
31 30 29 28
15 14 13 12
Table 31. mpubase Control Register Field Descriptions
Field
is the base memory address of the region identified by the
BASE BASE
and
INDEX
is the region index number.
INDEX INDEX
is the region access bit. When
D D
When = 0,
D
(10)
This field size is variable. Unused upper bits must be written as zero.
(11)
This field size is variable. Unused upper bits and unused lower bits must be written as zero.
Description
on each interrupt, disabling fast
status.PIE
is set to one, the processor keeps
ANI
set to one at the time of an interrupt, enabling fast
always reads as zero, disabling fast nested
ANI
is the ECC error exception enable bit. When
is the ECC enable bit. When
ECCEN
= 1, the Nios II processor
ECCEN
= 0, the MPU is disabled. In systems without an
PE
is always zero.
register works in conjunction with the
Bit Fields
27 26 25 24
11 10 9
(11)
BASE
Description
fields.
D
=1,
D INDEX
refers to an instruction region.
INDEX
is set to zero,
ANI
= 1, the
ECCEXE
= 0, the Nios II processor
=1, the MPU is
PE
mpuacc
23 22 21
(11)
BASE
8 7 6 5
0
refers to a data region.
Access Reset
Read/Write 0
Read/Write 0
Read/Write 0
Read/Write 0
register to set and
20 19 18 17
4 3 2 1
(10)
INDEX
Access Reset Availabl
e
Read/Write 0 Only
with
MPU
Read/Write 0 Only
with
MPU
Read/Write 0 Only
with
MPU
Nios II Processor Reference Guide
Available
Only with the
EIC interface
and shadow
register sets
Only with ECC
Only with ECC
Only with MPU
16
0
D
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