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4. Instantiating the Nios II Processor
NII-PRG | 2018.04.18
4.4.2. Arithmetic Implementation
This section is only available if you choose to manually select your multiply/shift/
rotate hardware.
•
32-bit multiply instruction implementation—You have three options for the
32-bit multiply instruction. Choosing the 1 32-bit multiplier option allocates all
resources to the 32-bit multiplier making it the resource for the 64-bit multiply
instruction and shift/rotate instruction.
Table 57.
32-bit multiply instruction implementation options
Performance
11 cycles
1 cycle
1 cycle
•
64-bit multiply instruction implementation— This option can only be used if
the 32-bit multiply instruction selection is set to the 3 16-bit multipliers option.
The Nios II only supports up to a 32 x 32 bit multiplication. The 64-bit option is
achieved by using the 32-bit multiplier along with the multiply extended
instructions (
Set Reference chapter of this manual.
Table 58.
64-bit multiply instruction implementation options
Performance
2 cycles
•
Shift/rotate instruction implementation—Platform Designer gives you the
option of either choosing non-pipelined or pipelined.
Table 59.
Shift/rotate instruction implementation options
Performance
2 - 11 cycles
1 cycle
Note:
Highly recommend to chose auto selection. Platform Designer will make the selections
according to the device family previously selected.
4.5. MMU and MPU Settings Tab
The MMU and MPU Settings tab presents settings for configuring the MMU and MPU
on the Nios II processor. You can select the features appropriate for your target
application.
Resources
Logic elements
3 16-bit multipliers
1 32-bit multipliers
,
,
mulxss
mulxsu
mulxuu
Resources
1 16-bit multiplier
Resources
Logic elements (non-pipelined)
Logic elements (pipelined)
Instruction
All 32-bit Multiply
All 32-bit Multiply
All 32-bit Multiply
), which can be found in the Instruction
Instruction
All 64-bit Multiply
Instructions
All Shift/Rotate
All Shift/Rotate
Nios II Processor Reference Guide
113
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