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3. Programming Model
NII-PRG | 2018.04.18
Field
Inject ECC error in DTCM1. Injection occurs on next store instruction
DTCM1
that writes this DTCM.
Inject ECC error in DTCM2. Injection occurs on next store instruction
DTCM2
that writes this DTCM.
Inject ECC error in DTCM3. Injection occurs on next store instruction
DTCM3
that writes this DTCM.
Inject ECC error in data cache victim line buffer RAM. Injection occurs
DC WB
on the first word written into the victim buffer RAM when a dirty line is
being written back.
Refer to "Working with ECC" for more information about when errors are injected.
Related Information
Working with ECC
3.4.3. Shadow Register Sets
The Nios II processor can optionally have one or more shadow register sets. A shadow
register set is a complete alternate set of Nios II general-purpose registers, which can
be used to maintain a separate runtime context for an interrupt service routine (ISR).
When shadow register sets are implemented,
currently in use. A Nios II core can have up to 63 shadow register sets. If n is the
configured number of shadow register sets, the shadow register sets are numbered
from 1 to n. Register set 0 is the normal register set.
A shadow register set behaves precisely the same as the normal register set. The
register set currently in use can only be determined by examining
Note:
When shadow register sets and the EIC interface are implemented on the Nios II core,
you must ensure that your software is built with the Nios II EDS version 9.0 or later.
Earlier versions have an implementation of the
with shadow register sets.
Shadow register sets are typically used in conjunction with the EIC interface. This
combination can substantially reduce interrupt latency.
For details of EIC interface usage, refer to the Exception Processing section.
System software can read from and write to any shadow register set by setting
status.PRS
For details of the
Reference chapter of the Nios II Processor Reference Handbook.
Related Information
•
Instruction Set Reference
•
Exception Processing
Description
on page 69
and using the
and
rdprs
and
instructions, refer to the Instruction Set
rdprs
wrprs
on page 169
on page 74
Access
Read/Write
Read/Write
Read/Write
Read/Write
indicates the register set
status.CRS
instruction that is incompatible
eret
instructions.
wrprs
Nios II Processor Reference Guide
Reset
Availabl
e
0
0
0
0
.
status.CRS
65
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