Intel NIOS II Owner Reference Manual page 82

The method for mapping interrupts to register sets is specific to the particular EIC
implementation.
Related Information
Requested Register Set
3.7.6.2. Internal Interrupt Controller
When the internal interrupt controller is implemented, a peripheral device can request
a hardware interrupt by asserting one of the Nios II processor's 32 interrupt-request
inputs,
irq0
of these conditions are true:
•
The
PIE
•
An interrupt-request input,
•
The corresponding bit n of the
Upon hardware interrupt, the processor clears the
interrupts, and performs the other steps outlined in the "Exception Processing Flow"
section of this chapter.
The value of the
pending. By peripheral design, an IRQ bit is guaranteed to remain asserted until the
processor explicitly responds to the peripheral.
Note: Although shadow register sets can be implemented in any Nios II/f processor, the
internal interrupt controller does not have features to take advantage of it as external
interrupt controllers do.
Nios II Processor Reference Guide
82
on page 81
through . A hardware interrupt is generated if and only if all three
irq31
bit of the control register is one.
status
n, is asserted.
irq
ienable
control register shows which interrupt requests (IRQ) are
ipending
3. Programming Model
control register is one.
bit to zero, disabling further
PIE
NII-PRG | 2018.04.18