Table of Contents
Advertisement
5. Nios II Core Implementation Details
NII-PRG | 2018.04.18
•
Provides optional hardware multiply, divide, and shift options to improve
arithmetic performance
•
Supports the addition of custom instructions
•
Optional ECC support for internal RAM blocks (data cache, data cache victim buffer
RAM, instruction and data tightly-coupled memories, instruction cache, MMU TLB,
and register file)
•
Supports the JTAG debug module
•
Supports optional JTAG debug module enhancements, including hardware
breakpoints and real-time trace
The following sections discuss the noteworthy details of the Nios II/f core
implementation. This document does not discuss low-level design issues or
implementation details that do not affect Nios II hardware or software designers.
5.2.2. Arithmetic Logic Unit
The Nios II/f core provides several arithmetic logic unit (ALU) options to improve the
performance of multiply, divide, and shift operations.
5.2.2.1. Multiply and Divide Performance
The Nios II/f core provides the following hardware multiplier options:
•
DSP Block—Includes DSP block multipliers available on the target device. This
option is available only on Intel FPGAs that have a hardware multiplier that
supports 32-bit multiplication.
•
Embedded Multipliers—Includes dedicated embedded multipliers available on the
target device. This option is available only on Intel FPGAs that have embedded
multipliers.
•
Logic Elements—Includes hardware multipliers built from logic element (LE)
resources.
•
None—Does not include multiply hardware. In this case, multiply operations are
emulated in software.
The Nios II/f core also provides a hardware divide option that includes LE-based divide
circuitry in the ALU.
Including an ALU option improves the performance of one or more arithmetic
instructions.
Note:
The performance of the embedded multipliers differ, depending on the target FPGA
family.
Table 62.
Hardware Multiply and Divide Details for the Nios II/f Core
ALU Option
No hardware multiply or
divide
Logic elements
Hardware Details
Multiply and divide
instructions generate an
exception
ALU includes 32 x 4-bit
multiplier
Cycles per
Result Latency
Instruction
–
–
11
+2
Supported
Cycles
Instructions
None
,
mul
muli
continued...
Nios II Processor Reference Guide
123
Advertisement
Table of Contents
