Ldhu / Ldhuio - Intel NIOS II Owner Reference Manual

8. Instruction Set Reference
NII-PRG | 2018.04.18
Related Information
Cache and Tightly-Coupled Memory

8.5.57. ldhu / ldhuio

Instruction
Operation
Assembler Syntax
Example
Description
Usage
Exceptions
Instruction Type
Instruction Fields
Table 104. ldhu
31 30 29
A
15 14 13
28 27 26 25
12 11 10 9
IMM16
load unsigned halfword from memory or I/O peripheral
rB 0x0000 : Mem16[rA + σ(IMM16)]
ldhu rB, byte_offset(rA)
ldhuio rB, byte_offset(rA)
ldhu r6, 100(r5)
Computes the effective byte address specified by the sum of
rA and the instruction's signed 16-bit immediate value.
Loads register rB with the memory halfword located at the
effective byte address, zero extending the 16-bit value to 32
bits. The effective byte address must be halfword aligned. If
the byte address is not a multiple of 2, the operation is
undefined.
In processors with a data cache, this instruction may
retrieve the desired data from the cache instead of from
memory. Use the
ldhuio
processors with a data cache,
and is guaranteed to generate an Avalon-MM data transfer.
In processors without a data cache,
For more information on data cache, refer to the Cache and
Tightly Coupled Memory chapter of the Nios II Software
Developer's Handbook.
Supervisor-only data address
Misaligned data address
TLB permission violation (read)
Fast TLB miss (data)
Double TLB miss (data)
MPU region violation (data)
I
= Register index of operand rA
A
= Register index of operand rB
B
= 16-bit signed immediate value
IMM16
Bit Fields
24 23 22 21
B
8 7 6 5
instruction for peripheral I/O. In
bypasses the cache
ldhuio
acts like
ldhuio ldhu
20 19 18 17
IMM16
4 3 2 1
0x0b
Nios II Processor Reference Guide
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16
0
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