Intel NIOS II Owner Reference Manual page 44

3.3.1.3. Region Index
Each region has an index ranging from zero to the number of regions of its region type
minus one. Index zero has the highest priority.
3.3.1.4. Region Size or Upper Address Limit
A Platform Designer generation-time option controls whether the amount of memory
in the region is defined by size or upper address limit. The size is an integer power of
two bytes. The limit is the highest address of the region plus one. The minimum
supported region size is 256 bytes but can be configured for larger minimum sizes to
save logic resources. The maximum supported region size equals the Nios II address
space (a function of the address ranges of slaves connected to the Nios II masters).
Any access outside of the Nios II address space is considered not to match any region
and triggers an MPU region violation exception.
When regions are defined by size, the size is encoded as a binary mask to facilitate
the following MPU region address range matching:
(address & region_mask) == region_base_address
When regions are defined by limit, the limit is encoded as an unsigned integer to
facilitate the following MPU region address range matching:
(address >= region_base) && (address < region_limit)
The region limit uses a less-than instead of a less-than-or-equal-to comparison
because less-than provides a more efficient implementation. The limit is one bit larger
than the address so that full address range may be included in a range. Defining the
region by limit results in slower and larger address range match logic than defining by
size but allows finer granularity in region sizes.
3.3.1.5. Access Permissions
The access permissions consist of execute permissions for instruction regions and
read/write permissions for data regions. Any instruction that performs a memory
access that violates the access permissions triggers an exception. Additionally, any
instruction that performs a memory access that does not match any region triggers an
exception.
3.3.1.6. Default Cacheability
The default cacheability specifies whether normal load and store instructions access
the data cache or bypass the data cache. The default cacheability is only present for
data regions. You can override the default cacheability by using the
instructions. The bit-31 cache and Peripheral Region featurs are available when the
MMU is not present.
Refer to the Cache Memory section for more information on cache bypass and
Peripheral Region.
Related Information
Cache Memory
Nios II Processor Reference Guide
44
on page 99
3. Programming Model
NII-PRG | 2018.04.18
or
ldwio stwio