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5. Nios II Core Implementation Details
NII-PRG | 2018.04.18
Divide
Shift/rotate (with hardware multiply using embedded multipliers)
Shift/rotate (with hardware multiply using LE-based multipliers)
Shift/rotate (without hardware multiply present)
All other instructions
For Multiply and Divide, the number of cycles depends on the hardware multiply or
divide option. Refer to "Arithmetic Logic Unit" and "Instruction and Data Caches" s for
details.
In the default Nios II/f configuration, instructions
flushp, wrctl, wrprs
present, they require five clock cycles:
•
MMU
•
MPU
•
Division exception
•
Misaligned load/store address exception
•
EIC port
•
Shadow register sets
Related Information
•
Data Cache
•
Instruction and Data Caches
•
Arithmetic Logic Unit
5.2.9. Exception Handling
The Nios II/f core supports the following exception types:
•
Hardware interrupts
•
Software trap
•
Illegal instruction
•
Unimplemented instruction
•
Supervisor-only instruction (MMU or MPU only)
•
Supervisor-only instruction address (MMU or MPU only)
•
Supervisor-only data address (MMU or MPU only)
•
Misaligned data address
•
Misaligned destination address
•
Division error
•
Error-correcting code (ECC)
•
Fast translation lookaside buffer (TLB) miss (MMU only)
Instruction
require four clock cycles. If any of the following options are
on page 126
on page 125
on page 123
Cycles
1
2
1 to 32
1
trap, break, eret, bret,
Nios II Processor Reference Guide
Penalties
Late result
Late result
Late result
Late result
131
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