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3. Programming Model
NII-PRG | 2018.04.18
Register
4
5
6
7
8
9
10
11
12
13
14
15
16–31
The following sections describe the nonreserved control registers.
Control registers report the status and change the behavior of the processor. Control
registers are accessed differently than the general-purpose registers. The special
instructions
registers and are only available in supervisor mode.
Note:
When writing to control registers, all undefined bits must be written as zero.
The Nios II architecture supports up to 32 control registers. All nonreserved control
registers have names recognized by the assembler.
Name
ipending
cpuid
Reserved
exception
pteaddr
tlbacc
tlbmisc
eccinj
badaddr
config
mpubase
mpuacc
Reserved
and
provide the only means to read and write to the control
rdctl
wrctl
Register Contents
Available only when the external interrupt controller
interface is not present. Otherwise reserved.
Pending internal interrupt bits
The ipending Register
Available only when the external interrupt controller
interface is not present. Otherwise reserved.
Unique processor identifier
Reserved
Refer to
The exception Register
Refer to
The pteaddr Register
Available only when the MMU is present. Otherwise
reserved.
Refer to
The tlbacc Register
Available only when the MMU is present. Otherwise
reserved.
Refer to
The tlbmisc Register
Available only when the MMU is present. Otherwise
reserved.
Refer to
The eccinj Register
Available only when ECC is present.
Refer to
The badaddr Register
Refer to
The config Register
on page 58
Available only when the MPU or ECC is present.
Otherwise reserved.
Refer to
The mpubase Register
Available only when the MPU is present. Otherwise
reserved.
Refer to
The mpuacc Register
Available only when the MPU is present. Otherwise
reserved.
Reserved
Nios II Processor Reference Guide
for MASK variations table.
47
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