Intel NIOS II Owner Reference Manual page 67

3. Programming Model
NII-PRG | 2018.04.18
The
sstatus
shadow register sets are implemented. There is one copy of
register set.
When the Nios II processor takes an interrupt, if a shadow register set is requested
(RRS = 0) and the MMU is not in exception handler mode (
processor copies
For details about RRS, refer to "Requested Register Set".
For details about
Exceptions Table.
Related Information
• The status Register
• Exceptions and Processor Status
• Requested Register Set
• The status Register
3.4.3.1.1. Changing Register Sets
Modifying
set. However, software cannot write to
insert the desired value into the saved copy of the
the
eret
• If the processor is currently running in the normal register set, insert the new
register set number in
• If the processor is currently running in a shadow register set, insert the new
register set number in
Before executing
external interrupt masks correctly to ensure that registers in the shadow register set
cannot be corrupted. If an interrupt is assigned to the register set, system software
must ensure that one of the following conditions is true:
• The ISR is written to preserve register contents.
• The individual interrupt is disabled. The method for disabling an individual external
interrupt is specific to the EIC implementation.
3.4.3.1.2. Stacks and Shadow Register Sets
Depending on system requirements, the system software can create a dedicated stack
for each register set, or share a stack among several register sets. If a stack is
shared, the system software must copy the stack pointer each time the register set
changes. Use the
register set and another register set.
3.4.3.2. Initialization with Shadow Register Sets
At initialization, system software must carry out the following tasks to ensure correct
software functioning with shadow register sets:
register is present in the Nios II core if both the EIC interface and
to
status sstatus
, refer to the Nios II Processor Status After Taking
status.EH
on page 48
on page 81
on page 48
immediately switches the Nios II processor to another register
status.CRS
instruction, as follows:
estatus.CRS
sstatus.CRS
to change the register set, system software must set individual
eret
instruction to copy the stack register between the current
rdprs
status.EH
.
on page 91
directly. To modify
status.CRS
register, and then execute
status
, and execute
eret
, and execute
eret
for each shadow
sstatus
= 0), the
status.CRS
.
.
Nios II Processor Reference Guide
,
67