Intel NIOS II Owner Reference Manual page 62

Table 35. MASK Region Size Encodings
MASK Encoding
0xFFFFFF
0xFFFFFE
0xFFFFFC
0xFFFFF8
0xFFFFF0
0xFFFFE0
0xFFFFC0
0xFFFF80
0xFFFF00
0xFFFE00
0xFFFC00
0xFFF800
0xFFF000
0xFFE000
0xFFC000
0xFF8000
0xFF0000
0xFE0000
0xFC0000
0xF80000
0xF00000
0xE00000
0xC00000
0x800000
0x000000
The
MASK
MASK = 0xFFFFFF << log2(region_size >> 8)
3.4.2.14.2. The LIMIT Field
When the amount of memory reserved for a region is defined by an upper address
limit, the
example, to achieve a memory range for byte addresses
256 byte minimum region size, the
(
0x4000 >> 6
field is one more bit than the number of bits of the
LIMIT
register, bit 31 of the
Nios II Processor Reference Guide
62
256 bytes
512 bytes
1 KB
2 KB
4 KB
8 KB
16 KB
32 KB
64 KB
128 KB
256 KB
512 KB
1 MB
2 MB
4 MB
8 MB
16 MB
32 MB
64 MB
128 MB
256 MB
512 MB
1 GB
2 GB
4 GB
field contains the following value, where
field specifies the upper address of the memory region plus one. For
LIMIT
) and the field is set to
LIMIT
register is available to the
mpuacc
Region Size
region_size
0x4000
field of the
BASE mpubase
(
0x50 0x5000 >> 8
LIMIT
3. Programming Model
NII-PRG | 2018.04.18
is in bytes:
to with a
0x4fff
register is set to
0x40
). Because the
field of the
BASE mpubase
field.