Intel NIOS II Owner Reference Manual page 116

Figure 11. Nios II Platform Designer JTAB Debug Tab
Soft processor cores such as the Nios II processor offer unique debug capabilities
beyond the features of traditional fixed processors. The soft nature of the Nios II
processor allows you to debug a system in development using a full-featured debug
core, and later remove the debug features to conserve logic resources. For the release
version of a product, you might choose to reduce the JTAG debug module
functionality, or remove it altogether.
Table 60. Debug Configuration Features
Feature
JTAG Target Connection
Download Software
Software Breakpoints
Hardware Breakpoints
Data Triggers
Instruction Trace
Data Trace
On-Chip Trace
Off-Chip Trace
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Connects to the processor through the standard JTAG pins on the Intel FPGA. This connection
provides the basic capabilities to start and stop the processor, and examine/edit registers and
memory.
Downloads executable code to the processor's memory via the JTAG connection.
Sets a breakpoint on instructions residing in RAM.
Sets a breakpoint on instructions residing in nonvolatile memory, such as flash memory.
Triggers based on address value, data value, or read or write cycle. You can use a trigger to
halt the processor on specific events or conditions, or to activate other events, such as
starting execution trace, or sending a trigger signal to an external logic analyzer. Two data
triggers can be combined to form a trigger that activates on a range of data or addresses.
Captures the sequence of instructions executing on the processor in real time.
Captures the addresses and data associated with read and write operations executed by the
processor in real time.
Stores trace data in on-chip memory.
Stores trace data in an external debug probe. Off-chip trace instantiates a PLL inside the
Nios II core. Off-chip trace requires a debug probe from Imagination Technologies or
Lauterbach GmbH.
4. Instantiating the Nios II Processor
Description
NII-PRG | 2018.04.18