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Exceptions
Instruction Type
Instruction Fields
31
30
29
0x1d
15
14
13
0x01
8.5.45. flushd
Instruction
Operation
Assembler Syntax
Example
Description
Usage
Nios II Processor Reference Guide
198
28
27
26
25
12
11
10
9
Misaligned destination address
Supervisor-only instruction
R
None
Bit Fields
24
23
22
21
0x1e
8
7
6
5
0
flush data cache line
Flushes the data cache line associated with address
rA + σ(IMM16).
flushd IMM16(rA)
flushd -100(r6)
If the Nios II processor implements a direct mapped data
cache,
writes the data cache line that is mapped to
flushd
the specified address back to memory if the line is dirty, and
then clears the data cache line. Unlike
writes the dirty data back to memory even when the
addressed data is not currently in the cache. This process
comprises the following steps:
•
Compute the effective address specified by the sum of rA
and the signed 16-bit immediate value.
•
Identify the data cache line associated with the
computed effective address. Each data cache effective
address comprises a
identifying the data cache line,
field and only uses the
cache line to clear.
•
Skip comparing the cache line tag with the effective
address to determine if the addressed data is currently
cached. Because
flushd
flushes the cache line regardless of whether the
flushd
specified data location is currently cached.
•
If the data cache line is dirty, write the line back to
memory. A cache line is dirty when one or more words of
the cache line have been modified by the processor, but
are not yet written to memory.
•
Clear the valid bit for the line.
If the Nios II processor core does not have a data cache,
the
instruction performs no operation.
flushd
Use
to write dirty lines back to memory even if the
flushd
addressed memory location is not in the cache, and then
flush the cache line. By contrast, refer to "flushda flush data
cache address", "initd initialize data cache line", and "initda
initialize data cache address" for other cache-clearing
options.
For more information on data cache, refer to the Cache and
Tightly Coupled Memory chapter of the Nios II Software
Developer's Handbook.
8. Instruction Set Reference
NII-PRG | 2018.04.18
20
19
18
17
C
4
3
2
1
0x3a
,
flushda
flushd
field and a
field. When
tag
line
ignores the
flushd
field to select the data
line
ignores the cache line tag,
continued...
16
0x01
0
tag
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