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Table 6.
Trigger Actions
Action
Break
External trigger
Trace on
Trace off
Trace sample
Arm
Note:
For the Trace sample triger action, only conditions on the data bus can trigger this
action.
2.7.5.1. Armed Triggers
The JTAG debug module provides a two-level trigger capability, called armed triggers.
Armed triggers enable the JTAG debug module to trigger on event B, only after event
A. In this example, event A causes a trigger action that enables the trigger for event
B.
2.7.5.2. Triggering on Ranges of Values
The JTAG debug module can trigger on ranges of data or address values on the data
bus. This mechanism uses two hardware triggers together to create a trigger condition
that activates on a range of values within a specified range.
2.7.6. Trace Capture
Trace capture refers to ability to record the instruction-by-instruction execution of the
processor as it executes code in real-time. The JTAG debug module offers the
following trace features:
•
Capture execution trace (instruction bus cycles).
•
Capture data trace (data bus cycles).
•
For each data bus cycle, capture address, data, or both.
•
Start and stop capturing trace in real time, based on triggers.
•
Manually start and stop trace under host control.
•
Optionally stop capturing trace when trace buffer is full, leaving the processor
executing.
•
Store trace data in on-chip memory buffer in the JTAG debug module. (This
memory is accessible only through the JTAG connection.)
•
Store trace data to larger buffers in an off-chip debug probe.
Certain trace features require additional licensing or debug tools from third-party
debug providers. For example, an on-chip trace buffer is a standard feature of the
Nios II processor, but using an off-chip trace buffer requires additional debug software
and hardware provided by Imagination Technologies
Nios II Processor Reference Guide
34
Halt execution and transfer control to the JTAG debug module.
Assert a trigger signal output. This trigger output can be used, for example, to trigger an external logic
analyzer.
Turn on trace collection.
Turn off trace collection.
Store one sample of the bus to trace buffer.
Enable an armed trigger.
2. Processor Architecture
NII-PRG | 2018.04.18
Description
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, LLC or Lauterbach GmbH.
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