Intel NIOS II Owner Reference Manual page 58

Table 26. badaddr Control Register Fields
31 30 29
15 14 13
Table 27. badaddr Control Register Field Descriptions
Field
contains the byte instruction address or data address
BADDR BADDR
associated with an exception when certain exceptions occur. The
Address column of the Nios II Exceptions Table lists which exceptions
write the
The
BADDR
or MPU is present, the
data addresses are always full 32-bit values. When an MMU is present, the
contains the virtual address.
If there is no MMU or MPU and the Nios II address space is less than 32 bits, unused
high-order bits are written and read as zero. If there is no MMU, bit 31 of a data
address (used to bypass the data cache) is always zero in the
Related Information
• Exception Overview
• Programming Model
3.4.2.12. The config Register
The
config
preserved during exception processing (in contrast to the information in the
register).
Table 28. config Control Register Fields
31 30 29
15 14 13
Nios II Processor Reference Guide
58
28 27 26 25
12 11 10 9
Description
field.
BADDR
field allows up to a 32-bit instruction address or data address. If an MMU
field is 32 bits because MMU and MPU instruction and
BADDR
on page 75
on page 36
register configures Nios II runtime behaviors that do not need to be
28 27 26 25
12 11 10 9
Reserved
Bit Fields
24 23 22 21
BADDR
8 7 6 5
BADDR
Bit Fields
24 23 22 21
Reserved
8 7 6 5
3. Programming Model
NII-PRG | 2018.04.18
20 19 18 17
4 3 2 1
Access Reset Availabl
Read 0 Only
with
Nios II/f
BADDR
field.
BADDR
status
20 19 18 17
4 3 2 1
ECCE ECCE ANI
XE N
16
0
e
field
16
0
PE