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Usage
Exceptions
Instruction Type
Instruction Fields
31
30
29
A
15
14
13
Related Information
•
Cache and Tightly-Coupled Memory
•
flushda
•
initda
•
flushd
Nios II Processor Reference Guide
202
28
27
26
25
12
11
10
9
IMM16
on page 199
on page 203
on page 198
clears the cache line regardless of whether the addressed
data is currently cached. This process comprises the
following steps:
•
Compute the effective address specified by the sum of rA
and the signed 16-bit immediate value.
•
Identify the data cache line associated with the
computed effective address. Each data cache effective
address comprises a
identifying the line,
uses the
field to select the data cache line to clear.
line
•
Skip comparing the cache line tag with the effective
address to determine if the addressed data is currently
cached. Because
initd
flushes the cache line regardless of whether the
initd
specified data location is currently cached.
•
Skip checking if the data cache line is dirty. Because
skips the dirty cache line check, data that has
initd
been modified by the processor, but not yet written to
memory is lost.
•
Clear the valid bit for the line.
If the Nios II processor core does not have a data cache,
the
instruction performs no operation.
initd
Use
after processor reset and before accessing data
initd
memory to initialize the processor's data cache. Use
with caution because it does not write back dirty data. By
contrast, refer to "flushd flush data cache line", "flushda
flush data cache address", and "initda initialize data cache
address" for other cache-clearing options. Intel recommends
using
only when the processor comes out of reset.
initd
For more information on data cache, refer to the Cache and
Tightly Coupled Memory chapter of the Nios II Software
Developer's Handbook.
Supervisor-only instruction
I
= Register index of operand rA
A
= 16-bit signed immediate value
IMM16
Bit Fields
24
23
22
21
0
8
7
6
5
8. Instruction Set Reference
NII-PRG | 2018.04.18
field and a
field. When
tag
line
ignores the
field and only
initd
tag
ignores the cache line tag,
initd
20
19
18
17
IMM16
4
3
2
1
0x33
16
0
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