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Table 105.
ldhuio
31
30
29
A
15
14
13
Related Information
Cache and Tightly-Coupled Memory
8.5.58. ldw / ldwio
Instruction
Operation
Assembler Syntax
Example
Description
Usage
Exceptions
Instruction Type
Instruction Fields
Nios II Processor Reference Guide
210
28
27
26
25
12
11
10
9
IMM16
Bit Fields
24
23
22
21
B
8
7
6
5
load 32-bit word from memory or I/O peripheral
rB
Mem32[rA + σ(IMM14)]
ldw rB, byte_offset(rA)
ldwio rB, byte_offset(rA)
ldw r6, 100(r5)
Computes the effective byte address specified by the sum of
rA and the instruction's signed 16-bit immediate value.
Loads register rB with the memory word located at the
effective byte address. The effective byte address must be
word aligned. If the byte address is not a multiple of 4, the
operation is undefined.
In processors with a data cache, this instruction may
retrieve the desired data from the cache instead of from
memory. Use the
ldwio
processors with a data cache,
and memory. Use the
ldwio
In processors with a data cache,
and is guaranteed to generate an Avalon-MM data transfer.
In processors without a data cache,
For more information on data cache, refer to the Cache and
Tightly Coupled Memory chapter of the Nios II Software
Developer's Handbook.
Supervisor-only data address
Misaligned data address
TLB permission violation (read)
Fast TLB miss (data)
Double TLB miss (data)
MPU region violation (data)
I
= Register index of operand rA
A
= Register index of operand rB
B
= 16-bit signed immediate value
IMM16
8. Instruction Set Reference
NII-PRG | 2018.04.18
20
19
18
17
IMM16
4
3
2
1
0x2b
instruction for peripheral I/O. In
bypasses the cache
ldwio
instruction for peripheral I/O.
bypasses the cache
ldwio
acts like
ldwio
ldw
16
0
.
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