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3. Programming Model
NII-PRG | 2018.04.18
The
status.IL
serviced. The processor services a maskable interrupt only if its requested interrupt
level is greater than
An ISR can make run-time adjustments to interrupt nesting by manipulating
status.IL
emption by another level 5 interrupt, it can set
To enable all external interrupts, set
interrupts, set
3.7.13.3. Masking Interrupts with the Internal Interrupt Controller
The
ienable
of the
ienable
. A value of one in bit n means that the corresponding
irq31
enabled; a bit value of zero means that the corresponding interrupt is disabled.
Refer to the "Exception Processing" section of this chapter for more information.
An ISR can adjust
to the "Handling Nested Exceptions" section of this chapter for more information.
Related Information
•
Handling Nested Exceptions
•
Exception Processing
3.7.13.4. Returning From Interrupt and Instruction-Related Exceptions
The
eret
You must ensure that when an exception handler modifies registers, they are restored
when it returns. This can be taken care of in either of the following ways:
•
In the case of ISRs, if the EIC interface and shadow register sets are
implemented, and the ISR has a dedicated register set, no software action is
required. The Nios II processor returns to the previous register set when it
executes
•
For details, refer to the "Nested Exceptions with an External Interrupt Controller"
section of this chapter.
•
In the case of noninterrupt exceptions, for ISRs in a system with the internal
interrupt controller, and for ISRs without a dedicated shadow register set, the
exception handler must save registers on entry and restore them on exit. Saving
the register contents on the stack is a typical, re-entrant implementation.
Note:
It is not necessary to save and restore the exception temporary (
When executing the
1. Restores the previous contents of
field controls what level of external maskable interrupts can be
.
status.IL
. For example, if an ISR is running at level 5, to temporarily allow pre-
to 63.
status.IL
register controls the handling of internal hardware interrupts. Each bit
register corresponds to one of the interrupt inputs,
so that IRQs of equal or lower priority are disabled. Refer
ienable
on page 94
on page 74
instruction is used to resume execution at the pre-exception address.
, which restores the register contents.
eret
instruction, the processor performs the following tasks:
eret
status.IL
to 0. To disable all external
status.IL
as follows:
status
to 4.
through
irq0
n interrupt is
irq
or
) register.
et
r24
Nios II Processor Reference Guide
97
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