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Table 13.
Control Register Names and Bits
Register
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16–31
The following sections describe the nonreserved control registers.
3.4.2.1. The status Register
The value in the
bits are set to predefined values at processor reset. Some bits are exclusively
status
used by and available only to certain features of the processor, such as the MMU, MPU
or external interrupt controller (EIC) interface.
Nios II Processor Reference Guide
48
Name
status
estatus
bstatus
ienable
ipending
cpuid
Reserved
exception
pteaddr
tlbacc
tlbmisc
eccinj
badaddr
config
mpubase
mpuacc
Reserved
register determines the state of the Nios II processor. All
status
Register Contents
Refer to
The status Register
on page 48
Refer to
The estatus Register
Refer to
The bstatus Register
Internal interrupt-enable bits
The ienable Register
Available only when the external interrupt controller
interface is not present. Otherwise reserved.
Pending internal interrupt bits
The ipending Register
Available only when the external interrupt controller
interface is not present. Otherwise reserved.
Unique processor identifier
Reserved
Refer to
The exception Register
Refer to
The pteaddr Register
Available only when the MMU is present. Otherwise
reserved.
Refer to
The tlbacc Register
Available only when the MMU is present. Otherwise
reserved.
Refer to
The tlbmisc Register
Available only when the MMU is present. Otherwise
reserved.
Refer to
The eccinj Register
Available only when ECC is present.
Refer to
The badaddr Register
Refer to
The config Register
on page 58
Available when the MPU or ECC is present. Otherwise
reserved.
Refer to
The mpubase Register
Available only when the MPU is present. Otherwise
reserved.
Refer to
The mpuacc Register
Available only when the MPU is present. Otherwise
reserved.
Reserved
3. Programming Model
NII-PRG | 2018.04.18
on page 50
for MASK variations table.
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