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Note:
All noninterrupt exception handlers must run in the normal register set.
Clearing the
present, clearing the
Note:
Nonmaskable interrupts (NMIs) are not affected by
while processing a reset exception.
Invalidating the reset cache line guarantees that instruction fetches for reset code
comes from uncached memory.
Aside from the instruction cache line associated with the reset vector, the contents of
the cache memories are indeterminate after reset. To ensure cache coherency after
reset, the reset handler located at the reset vector must immediately initialize the
instruction cache. Next, either the reset handler or a subsequent routine should
proceed to initialize the data cache.
The reset state is undefined for all other system components, including but not limited
to:
•
General-purpose registers, except for
is permanently zero.
•
Control registers, except for
remaining fields are reset to 0.
•
Instruction and data memory.
•
Cache memory, except for the instruction cache line associated with the reset
vector.
•
Peripherals. Refer to the appropriate peripheral data sheet or specification for
reset conditions.
•
Custom instruction logic
•
Nios II C-to-hardware (C2H) acceleration compiler logic.
For more information refer to the Nios II Custom Instruction User Guide for reset
conditions.
Related Information
Nios II Custom Instruction User Guide
3.7.5. Break Exceptions
A break is a transfer of control away from a program's normal flow of execution for the
purpose of debugging. Software debugging tools can take control of the Nios II
processor via the JTAG debug module.
Break processing is the means by which software debugging tools implement debug
and diagnostic features, such as breakpoints and watchpoints. Break processing is a
type of exception processing, but the break mechanism is independent from general
exception processing. A break can occur during exception processing, enabling debug
tools to debug exception handlers.
Nios II Processor Reference Guide
78
field disables maskable interrupts. If the MMU or MPU is
status.PIE
field forces the processor into supervisor mode.
status.U
status
status.PIE
(
) in the normal register set, which
zero
r0
.
is reset to 1, and the
status.RSIE
3. Programming Model
NII-PRG | 2018.04.18
, and can be taken
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