Tlb Organization - Intel NIOS II Owner Reference Manual

3. Programming Model
NII-PRG | 2018.04.18
the Avalon switch fabric. Bit 31 is not used to specify data cacheability, as it is in
Nios II cores without MMUs. Virtual memory partitions that bypass the TLB have a
default data cacheability property, as described in the above table, Virtual Memory
Partitions. For partitions that are mapped through the TLB, data cacheability is
controlled by the TLB on a per-page basis.
Non-I/O load and store instructions use the default data cacheability property. I/O
load and store instructions are always noncacheable, so they ignore the default data
cacheability property.

3.2.4. TLB Organization

A TLB functions as a cache for the operating system's page table. In Nios II processors
with an MMU, one main TLB is shared by instruction and data accesses. The TLB is
stored in on-chip RAM and handles translations for instruction fetches and instructions
that perform data accesses.
The TLB is organized as an n-way set-associative cache. The software specifies the
way (set) when loading a new entry.
Note: You can configure the number of TLB entries and the number of ways (set
associativity) of the TLB with the Nios II Processor parameter editor in Platform
Designer. By default, the TLB is a 16-way cache. The default number of entries
depends on the target device, as follows:
• Cyclone III
For more information, refer to the Instantiating the Nios II Processor chapter of
the Nios II Processor Reference Handbook.
The operating system software is responsible for guaranteeing that multiple TLB
entries do not map the same virtual address. The hardware behavior is undefined
when multiple entries map the same virtual address.
Each TLB entry consists of a tag and data portion. This is analogous to the tag and
data portion of instruction and data caches.
Refer to the Nios II Core Implementation Details chapter of the Nios II Processor
Reference Handbook for information about instruction and data caches.
The tag portion of a TLB entry contains information used when matching a virtual
address to a TLB entry.
Table 9. TLB Tag Portion Contents
Field Name
VPN
PID
G
The TLB data portion determines how to translate a matching virtual address to a
physical address.
® ®
, Stratix III , Stratix IV—256 entries, requiring one M9K RAM
is the virtual page number field. This field is compared with the top 20 bits of the virtual
VPN
address.
is the process identifier field. This field is compared with the value of the current process
PID
identifier stored in the
tlbmisc
size is configurable in the Nios_II Processor parameter editor, and can be between 8 and 14 bits.
is the global flag. When = 1, the
G G
Description
control register, effectively extending the virtual address. The field
is ignored in the TLB lookup.
PID
Nios II Processor Reference Guide
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