Intel NIOS II Owner Reference Manual page 66

3.4.3.1. The sstatus Register
The value in the
external interrupt handling. The value of
Some bits are exclusively used by and available only to certain features of the
processor.
The
sstatus
shadow register set. The normal register set does not have an
each shadow register set has a separate
Table 40. sstatus Control Register Fields
31 30 29
SRS
15 14 13
CRS
Table 41. sstatus Control Register Field Descriptions
Bit
(13)
SRS
RSIE
NMI
PRS
CRS
IL
IH
EH
U
PIE
(13)
If the EIC interface and shadow register sets are not present,
processor behaves accordingly.
(14)
Refer to the status Control Register Field Descriptions Table
Nios II Processor Reference Guide
66
register preserves the state of the Nios II processor during
sstatus
register is physically stored in general-purpose register
28 27 26 25
Reserved
12 11 10 9
Description
is the switched register set bit. The
SRS
processor sets to 1 when an external
SRS
interrupt occurs, if the interrupt required the
processor to switch to a different register set.
is the register set interrupt-enable bit.
RSIE
When set to 1, this bit allows the processor to
service external interrupts requesting the
register set that is currently in use. When set
to 0, this bit disallows servicing of such
interrupts.
is the nonmaskable interrupt mode bit.
NMI
The processor sets to 1 when it takes a
NMI
nonmaskable interrupt.
(14)
(14)
(14)
(14)
(14)
(14)
(14)
is undefined at processor reset.
sstatus
register.
sstatus
Bit Fields
24 23 22 21
RSIE NMI
8 7 6 5
IL
Access
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
SRS
3. Programming Model
NII-PRG | 2018.04.18
in each
r30
register, but
sstatus
20 19 18 17
PRS
4 3 2 1
IH EH U
Reset Available
Undefined EIC interface
and shadow
register sets
only
(14)
Undefined
(14)
Undefined
(14)
Undefined
(14)
Undefined
(14)
Undefined
(14)
Undefined
(14)
Undefined
(14)
Undefined
(14)
Undefined
always reads as 0, and the
16
0
PIE