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8. Instruction Set Reference
NII-PRG | 2018.04.18
Table 110.
sth
31
30
29
A
15
14
13
Table 111.
sthio
31
30
29
A
15
14
13
8.5.89. stw / stwio
Instruction
Operation
Assembler Syntax
Example
Description
Usage
Exceptions
Instruction Type
Instruction Fields
28
27
26
25
12
11
10
9
IMM16
28
27
26
25
12
11
10
9
IMM16
= Register index of operand rB
B
= 16-bit signed immediate value
IMM16
Bit Fields
24
23
22
21
B
8
7
6
5
Bit Fields
24
23
22
21
B
8
7
6
5
store word to memory or I/O peripheral
Mem32[rA + σ(IMM16)]
stw rB, byte_offset(rA)
stwio rB, byte_offset(rA)
stw r6, 100(r5)
Computes the effective byte address specified by the sum of
rA and the instruction's signed 16-bit immediate value.
Stores rB to the memory location specified by the effective
byte address. The effective byte address must be word
aligned. If the byte address is not a multiple of 4, the
operation is undefined.
In processors with a data cache, this instruction may not
generate an Avalon-MM data transfer immediately. Use the
instruction for peripheral I/O. In processors with a
stwio
data cache,
bypasses the cache and is guaranteed to
stwio
generate an Avalon-MM bus cycle. In processors without a
data cache,
acts like
stwio
Supervisor-only data address
Misaligned data address
TLB permission violation (write)
Fast TLB miss (data)
Double TLB miss (data)
MPU region violation (data)
I
= Register index of operand rA
A
= Register index of operand rB
B
= 16-bit signed immediate value
IMM16
20
19
18
17
IMM16
4
3
2
1
0x0d
20
19
18
17
IMM16
4
3
2
1
0x2d
rB
.
stw
Nios II Processor Reference Guide
16
0
16
0
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