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3. Programming Model
NII-PRG | 2018.04.18
The exception handler can examine
the processor. When returning from an exception, the
pre-exception value of
copying either
status.CRS
Refer to the Exception Processing section for more information.
Related Information
•
Exception Processing
•
The sstatus Register
3.4.2.3. The bstatus Register
The
bstatus
exception processing.
Table 17.
btatus Control Register Fields
31
30
29
15
14
13
CRS
All fields in the
The Status Control Register Field Description table describes the details of the fields
defined in the
When a break occurs, the value of the
bstatus
break. The
Refer to the Processing a Break section for more information.
Related Information
Processing a Break
3.4.2.4. The ienable Register
The
ienable
of the
ienable
. A value of one in bit n means that the corresponding
irq31
enabled; a bit value of zero means that the corresponding interrupt is disabled. Refer
to the Exception Processing section for more information.
Note:
When the internal interrupt controller is not implemented, the value of the
register is always 0.
Related Information
Exception Processing
. The instruction restores the pre-exception value by
status
or
estatus
sstatus
.
on page 74
on page 66
register holds a saved copy of the
28
27
26
25
Reserved
12
11
10
9
register have read/write access. All fields reset to 0.
bstatus
register.
bstatus
, the debugger can restore the
instruction causes the processor to copy
bret
on page 79
register controls the handling of internal hardware interrupts. Each bit
register corresponds to one of the interrupt inputs,
on page 74
to determine the pre-exception status of
estatus
eret
back to
, depending on the value of
status
status
Bit Fields
24
23
22
21
RSIE
NMI
8
7
6
5
IL
register is copied into
status
register to the value prior to the
status
instruction restores the
register during break
20
19
18
17
PRS
4
3
2
1
IH
EH
U
. Using
bstatus
back to
bstatus
status
through
irq0
n interrupt is
irq
ienable
Nios II Processor Reference Guide
16
0
PIE
.
51
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