Intel NIOS II Owner Reference Manual page 19

2. Processor Architecture
NII-PRG | 2018.04.18
Feature
Double
Exception Invalid operation
conditions
Division by zero
Overflow
Inexact
Underflow
Rounding Modes Round to nearest
Round toward
zero
Round toward
+infinity
Round toward –
infinity
NaN Quiet
Signaling
Subnormal
(denormalized)
numbers
Software
exceptions
Status flags
Note: The FPH2 component also supports faithful rounding, which is not an IEEE 754-defined
rounding mode. Faithful rounding rounds results to either the upper or lower nearest
single-precision numbers. Therefore, the result produced is one of two possible values
and the choice between the two is not defined. The maximum error of faithful
rounding is 1 unit in the last place (ulp). Errors may not be evenly distributed.
(2)
This operation is not fully compliant with IEEE 754-2008.
Floating Point Hardware
Implementation with IEEE
754-1985
Not implemented. Double precision
operations are implemented in
software.
Result is Not a Number (NaN)
Result is ±infinity
Result is ±infinity
Result is a normal number
Result is ±0
Implemented
Not implemented
Not implemented
Not implemented
Implemented
Not implemented
Subnormal operands are treated as
zero. The FPH2 custom instructions do
not generate subnormal numbers.
Not implemented. IEEE 754-1985
exception conditions are detected and
handled as described elsewhere in this
table.
Not implemented. IEEE 754-1985
exception conditions are detected and
handled as described elsewhere in this
table.
Floating Point Hardware 2
Implementation with IEEE
754-2008
Not implemented. Double precision
operations are implemented in
software.
Result is Not a Number (NaN)
Result is ±infinity
Result is ±infinity
Result is a normal number
Result is ±0
Implemented (roundTiesToAway mode)
Implemented (truncation mode)
Not implemented
Not implemented
No distinction is made between
signaling and quiet NaNs as input
operands. A result that produces a NaN
may produce either a signaling or quiet
NaN.
• The comparison, minimum,
maximum, negate, and absolute
operations support subnormal
numbers.
• The add, subtract, multiply, divide,
square root, and float to integer
operations do NOT support
subnormal numbers. Subnormal
operands are treated as signed
zero. The FPH1 custom instructions
do not generate subnormal
(2)
numbers.
• The integer to float operation
cannot create subnormal numbers.
Not implemented. IEEE 754-2008
exception conditions are detected and
handled as described elsewhere in this
(2)
table.
Not implemented. IEEE 754-2008
exception conditions are detected and
handled as described elsewhere in this
(2)
table.
Nios II Processor Reference Guide
19