Table of Contents
Advertisement
3. Programming Model
NII-PRG | 2018.04.18
3.4.2.14.3. The MT Flag
The
flag determines the default memory type of an MPU data region. . The
MT
only applies to data regions. For instruction regions, the
for instruction regions and is always read as 0.
When data cacheability is enabled on a data region, a data access to that region can
be cached, if a data cache is present in the system. You can override the default
cacheability and force an address to noncacheable with an
instruction. The encoding of the MT field is setup to be backwards-compatible with the
Nios II Classic core MPU where bit 5 of MPUACC contains the cacheable bit (0 = non-
cacheable, 1 = cacheable) and bit 6 is zero.
Note:
The bit 31 cache bypass and peripheral region features are supported when the MPU is
present. Refer to the Cache memory section for more information on cache bypass.
3.4.2.14.4. The PERM Field
The
PERM
Table 36.
Instruction Region Permission Values
Value
0
1
2
Table 37.
Data Region Permission Values
Value
0
1
2
4
5
6
Note:
Unlisted table values are reserved and must not be used. If you use reserved values,
the resulting behavior is undefined.
3.4.2.14.5. The RD Flag
Setting the
when a
wrctl
Read and Write Operations section for more information. The
when read by a
Related Information
MPU Region Read and Write Operations
field specifies the allowed access permissions.
Supervisor Permissions
None
Execute
Execute
Supervisor Permissions
None
Read
Read
Read/Write
Read/Write
Read/Write
flag signifies that an MPU region read operation should be performed
RD
instruction is issued to the
instruction.
rdctl
bit must be written with 0
MT
ldwio
None
None
Execute
None
None
Read
None
Read
Read/Write
register. Refer to the MPU Region
mpuacc
RD
on page 68
Nios II Processor Reference Guide
flag
MT
or
stwio
User Permissions
User Permissions
flag always returns 0
63
Advertisement
Table of Contents
