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3. Programming Model
NII-PRG | 2018.04.18
Table 14.
status Control Register Fields
31
30
29
28
Reserved
15
14
13
12
CRS
Table 15.
status Control Register Field Descriptions
Bit
is the register set interrupt-enable bit. When set to 1, this bit
RSIE
RSIE
allows the processor to service external interrupts requesting the
register set that is currently in use. When set to 0, this bit disallows
servicing of such interrupts.
is the nonmaskable interrupt mode bit. The processor sets
NMI
NMI
1 when it takes a nonmaskable interrupt.
is the previous register set field. The processor copies the
PRS
PRS
field to the
•
In a processor with no MMU, on any exception
•
In a processor with an MMU, on one of the following:
Break exception
Nonbreak exception when
The processor copies
status
The number of significant bits in the
on the number of shadow register sets implemented in the Nios II
core. The value of
is the number of implemented register sets. The processor core
implements the number of significant bits needed to represent
n-1. Unused high-order bits are always read as 0, and must be
written as 0.
1 Ensure that system software writes only valid register set
numbers to the
unimplemented register set number.
is the current register set field.
CRS
CRS
currently in use. Register set 0 is the normal register set, while
register sets 1 and higher are shadow register sets. The processor
sets
to zero on any noninterrupt exception.
CRS
The number of significant bits in the
the number of shadow register sets implemented in the Nios II core.
Unused high-order bits are always read as 0, and must be written as
0.
is the interrupt level field. The
IL
IL
external maskable interrupts can be serviced. The processor services
a maskable interrupt only if its requested interrupt level is greater
than
.
IL
(6)
When this field is unimplemented, the field value always reads as 1, and the processor
behaves accordingly.
(7)
The
field is read-only. For information about manually changing register sets, refer to the
CRS
External Interrupt Controller Interface section.
Bit Fields
27
26
25
24
11
10
9
8
Description
field upon one of the following events:
PRS
is zero
status.EH
to
immediately after copying the
CRS
PRS
register to
,
or
estatus
bstatus
CRS
and
can range from 0 to n-1, where n
CRS
PRS
field. Processor behavior is undefined with an
PRS
indicates which register set is
CRS
and
CRS
field controls what level of
IL
23
22
21
20
RSIE
NMI
7
6
5
4
IL
Access
Read/Write
to
Read
NMI
Read/Write
CRS
.
sstatus
and
fields depends
PRS
Read
fields depends on
PRS
Read/Write
Nios II Processor Reference Guide
19
18
17
16
PRS
3
2
1
0
IH
EH
U
PIE
Reset
Available
1
EIC interface and
shadow register sets
(6)
only
0
EIC interface only
0
Shadow register sets
(9)
only
(7)
0
Shadow register sets
(9)
only
0
EIC interface only
49
(9)
(9)
continued...
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