Intel NIOS II Owner Reference Manual page 86

3.7.7.7. Supervisor-Only Data Address
When your system contains an MMU and the processor is in user mode (
), any attempt to access a supervisor-only data address results in a supervisor-only
1
data address exception. Instructions that can cause a supervisor-only data address
exception are all loads, all stores, and
This exception is implemented only in Nios II processors that include the MMU.
3.7.7.8. Misaligned Data Address
The Nios II processor can check for misaligned data addresses of load and store
instructions and generate an exception when a misaligned data address is
encountered. When your system contains an MMU or MPU, misaligned data address
checking is always on. When no MMU or MPU is present, you have the option to have
the processor check for misaligned data addresses.
For information about controlling this option, refer to the Instantiating the Nios II
Processor chapter of the Nios II Processor Reference Handbook.
A data address is considered misaligned if the byte address is not a multiple of the
width of the load or store instruction data width (four bytes for word, two bytes for
half-word). Byte load and store instructions are always aligned so never take a
misaligned address exception.
Related Information
Programming Model
3.7.7.9. Misaligned Destination Address
The Nios II processor can check for misaligned destination addresses of the
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misaligned destination address is encountered. When your system contains an MMU or
MPU, misaligned destination address checking is always on. When no MMU or MPU is
present, you have the option to have the processor check for misaligned destination
addresses.
For information about controlling this option, refer to the Instantiating the Nios II
Processor chapter of the Nios II Processor Reference Handbook.
A destination address is considered misaligned if the target byte address of the
instruction is not a multiple of four.
Related Information
Programming Model
3.7.7.10. Division Error
The Nios II processor can check for division errors and generate an exception when a
division error is encountered.
Nios II Processor Reference Guide
86
on page 36
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on page 36
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3. Programming Model
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