Table Of Contents - Intel NIOS II Owner Reference Manual

Contents
1. Introduction................................................................................................................... 8
1.1. Nios II Processor System Basics.............................................................................. 8
1.2. Getting Started with the Nios II Processor.................................................................9
1.3. Customizing Nios II Processor Designs....................................................................10
1.4. Configurable Soft Processor Core Concepts..............................................................11
1.4.1. Configurable Soft Processor Core............................................................... 11
1.4.2. Flexible Peripheral Set and Address Map......................................................11
1.4.3. Automated System Generation.................................................................. 12
1.5. Intel FPGA IP Evaluation Mode............................................................................... 13
1.6. Introduction Revision History.................................................................................13
2. Processor Architecture..................................................................................................14
2.1. Processor Implementation.....................................................................................15
2.2. Register File........................................................................................................ 16
2.3. Arithmetic Logic Unit............................................................................................ 17
2.3.1. Unimplemented Instructions......................................................................17
2.3.2. Custom Instructions................................................................................. 17
2.3.3. Introduction to Nios II Floating Point Custom Instructions..............................18
2.4. Reset and Debug Signals...................................................................................... 21
2.5. Exception and Interrupt Controllers........................................................................ 22
2.5.1. Exception Controller................................................................................. 22
2.5.2. EIC Interface...........................................................................................23
2.5.3. Internal Interrupt Controller...................................................................... 23
2.6. Memory and I/O Organization................................................................................24
2.6.1. Instruction and Data Buses....................................................................... 25
2.6.2. Cache Memory.........................................................................................27
2.6.3. Tightly-Coupled Memory........................................................................... 29
2.6.4. Address Map........................................................................................... 30
2.6.5. Memory Management Unit.........................................................................30
2.6.6. Memory Protection Unit............................................................................ 31
2.7. JTAG Debug Module............................................................................................. 32
2.7.1. JTAG Target Connection............................................................................ 32
2.7.2. Download and Execute Software................................................................ 33
2.7.3. Software Breakpoints............................................................................... 33
2.7.4. Hardware Breakpoints.............................................................................. 33
2.7.5. Hardware Triggers....................................................................................33
2.7.6. Trace Capture..........................................................................................34
2.8. Processor Architecture Revision History...................................................................35
3. Programming Model...................................................................................................... 36
3.1. Operating Modes..................................................................................................36
3.1.1. Supervisor Mode...................................................................................... 36
3.1.2. User Mode.............................................................................................. 37
3.2. Memory Management Unit.................................................................................... 37
3.2.1. Recommended Usage............................................................................... 37
3.2.2. Memory Management............................................................................... 38
3.2.3. Address Space and Memory Partitions.........................................................39
3.2.4. TLB Organization..................................................................................... 41
Nios II Processor Reference Guide
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Contents