Advanced Features Tab; Ecc - Intel NIOS II Owner Reference Manual

4. Instantiating the Nios II Processor
NII-PRG | 2018.04.18
The Include debugreq and debugack signals debug signals setting provides the
following functionality. When on, the Nios II processor includes debug request and
acknowledge signals. These signals let another device temporarily suspend the Nios II
processor for debug purposes. The signals are exported to the top level of your
Platform Designer system.
For more information about the debug signals, refer to the Processor Architecture
chapter of the Nios II Processor Reference Handbook.
You can set the onchip trace buffer size to sizes from 128 to 64K trace frames, using
OCI Onchip Trace. Larger buffer sizes consume more on-chip M4K RAM blocks. Every
M4K RAM block can store up to 128 trace frames.
Related Information
Processor Architecture

4.7. Advanced Features Tab

Figure 12. Nios II Platform Designer Advanced Features Tab

4.7.1. ECC

ECC is only available for the Nios II/f core and provides ECC support for Nios II
internal RAM blocks, such as instruction cache, MMU TLB, and register file. The
SECDED ECC algorithm is based on Hamming codes, which detect 1 or 2 bit errors and
corrects 1 bit errors. If the Nios II processor does not attempt to correct any errors
and only detects them, the ECC algorithm can detect 3 bit errors.
Refer to "ECC" section in the Nios II Core Implementation Details chapter for more
information about ECC support in the Nios II/f core.
on page 14
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