Intel NIOS II Owner Reference Manual page 4

4.2.3. Fast TLB Miss Exception Vector.................................................................108
4.3. Caches and Memory Interfaces Tab.......................................................................109
4.3.1. Instruction Cache................................................................................... 110
4.3.2. Flash Accelerator....................................................................................111
4.3.3. Data Cache........................................................................................... 111
4.3.4. Tightly-coupled Memories........................................................................111
4.3.5. Peripheral Region................................................................................... 112
4.4. Arithmetic Instructions Tab..................................................................................112
4.4.1. Arithmetic Instructions............................................................................112
4.4.2. Arithmetic Implementation...................................................................... 113
4.5. MMU and MPU Settings Tab................................................................................. 113
4.5.1. MMU.....................................................................................................114
4.5.2. MPU..................................................................................................... 115
4.6. JTAG Debug Tab.................................................................................................115
4.7. Advanced Features Tab....................................................................................... 117
4.7.1. ECC......................................................................................................117
4.7.2. Interrupt Controller Interfaces................................................................. 118
4.7.3. Shadow Register Sets............................................................................. 118
4.7.4. Reset Signals.........................................................................................118
4.7.5. CPU ID Control Register Value..................................................................119
4.7.6. Generate Trace File.................................................................................119
4.7.7. Exception Checking................................................................................ 119
4.7.8. Branch Prediction................................................................................... 120
4.7.9. RAM Memory Protection.......................................................................... 120
4.8. The Quartus Prime IP File....................................................................................120
4.9. Instantiating the Nios II Processor Revision History.................................................120
5. Nios II Core Implementation Details...........................................................................121
5.1. Device Family Support........................................................................................ 121
5.2. Nios II/f Core.................................................................................................... 122
5.2.1. Overview.............................................................................................. 122
5.2.2. Arithmetic Logic Unit.............................................................................. 123
5.2.3. Memory Access...................................................................................... 124
5.2.4. Tightly-Coupled Memory......................................................................... 127
5.2.5. Memory Management Unit.......................................................................128
5.2.6. Memory Protection Unit...........................................................................128
5.2.7. Execution Pipeline.................................................................................. 129
5.2.8. Instruction Performance.......................................................................... 130
5.2.9. Exception Handling.................................................................................131
5.2.10. ECC.................................................................................................... 133
5.2.11. JTAG Debug Module.............................................................................. 134
5.3. Nios II/s Core.................................................................................................... 135
5.3.1. Overview.............................................................................................. 135
5.3.2. Arithmetic Logic Unit.............................................................................. 135
5.3.3. Memory Access...................................................................................... 137
5.3.4. Tightly-Coupled Memory......................................................................... 138
5.3.5. Execution Pipeline.................................................................................. 138
5.3.6. Instruction Performance.......................................................................... 139
5.3.7. Exception Handling.................................................................................140
5.3.8. JTAG Debug Module................................................................................140
5.4. Nios II/e Core....................................................................................................140
Nios II Processor Reference Guide
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