Intel NIOS II Owner Reference Manual page 87

3. Programming Model
NII-PRG | 2018.04.18
The division error exception detects divide instructions that produce a quotient that
can't be represented. The two cases are divide by zero and a signed division that
divides the largest negative number -2147483648 (0x80000000) by -1 (0xffffffff).
Division error detection is only available if divide instructions are supported by
hardware.
Related Information
Programming Model
3.7.7.11. Fast TLB Miss
Fast TLB miss exceptions are implemented only in Nios II processors that include the
MMU. The MMU has a special exception vector (fast TLB miss), specified with the Nios
II Processor parameter editor in Platform Designer, specifically to handle TLB miss
exceptions quickly. Whenever the processor cannot find a TLB entry matching the VPN
(optionally extended by a process identifier), the result is a TLB miss exception. At the
time of the exception, the processor first checks
no other exception is already in process, so the processor considers the TLB miss a
fast TLB miss, sets
exception handler (rather than to the general exception handler).
There are two kinds of fast TLB miss exceptions:
• Fast TLB miss (instruction)—Any instruction fetch can cause this exception.
•
Fast TLB miss (data)—Load, store,
this exception.
The fast TLB miss exception handler can inspect the
which kind of fast TLB miss exception occurred.
3.7.7.12. Double TLB Miss
Double TLB miss exceptions are implemented only in Nios II processors that include
the MMU. When a TLB miss exception occurs while software is currently processing an
exception (that is, when
Specifically, whenever the processor cannot find a TLB entry matching the VPN
(optionally extended by a process identifier) and
double TLB miss exception. The most common scenario is that a double TLB miss
exception occurs during processing of a fast TLB miss exception. The processor
preserves register values from the original exception and transfers control to the
general exception handler which processes the newly-generated exception.
There are two kinds of double TLB miss exceptions:
• Double TLB miss (instruction)—Any instruction fetch can cause this exception.
•
Double TLB miss (data)—Load, store,
cause this exception.
The general exception handler can inspect either the
tlbmisc
on page 36
. to one, and transfers control to the fast TLB miss
status EH
status.EH
. field to determine which kind of double TLB miss exception occurred.
D
status.EH
, and
initda flushda
tlbmisc
= 1), a double TLB miss exception is generated.
status.EH
, and
initda flushda
exception
. When = 0,
status.EH
instructions can cause
. field to determine
D
= , the result is a
1
instructions can
. or
CAUSE
Nios II Processor Reference Guide
87